Electrically erasable and programmable non-volatile memory (EEPROM), wherein write pulses can be interrupted by subsequently received read requests

• US 5,287,469 A
• Filed: 12/27/1989
• Issued: 02/15/1994
• Est. Priority Date: 12/27/1988
• Status: Expired due to Fees

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Tsuboi, Toshihide
• Primary Examiner(s): Lee, Thomas C.
• Assistant Examiner(s): Von Buhr, Maria N.
• Application Number:
  US07/457,245
• Time in Patent Office: 1,511 Days
• Field of Search: 395/275, 395/800, 395/425, 395/725, 364/DIG. 1, 364/DIG. 2, 365/189.05, 365/189.07
• US Class Current: 711/103
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 16/32 Timing circuits
• CPC Class Codes: G11C 2216/20 Suspension of programming or erasing cells in an array in order to read other cells in it

Abstract

A microcomputer having an electrically erasable and programmable nonvolatile memory into which data is written without prolonging the data write processing time, even when a data read request is issued during the data write processing operation. The microcomputer includes a data erasing/writing/reading control circuit which coordinates the writing and reading of data to and from memory. The control circuit includes a timer for counting a predetermined number of counts during the data write process corresponding to the time period required to positively write data into the memory. If a data read request occurs during the data write process, the counting of the timer is suspended while the data is read out from the memory. After the data read process is completed, the data write process is resumed, and the timer continues counting toward the predetermined count from the count at which it was suspended. When the timer reaches the predetermined count, the data has been positively written into memory, and the data write process is terminated.

Claims

1. A microcomputer comprising an electrically erasable and programmable nonvolatile memory, a central processing unit for executing a program and issuing a data write request and a data read request to said nonvolatile memory, said data write request including a write address and write data and said read request including a read address, and a control circuit coupled to said nonvolatile memory and said central processing unit, said control circuit including timer means for preforming a time-counting operation to generate an operation end signal, first means responsive to said data write request for performing a data write process in which data stored in a first memory cell of said nonvolatile memory designated by said write address is first erased by applying a high voltage and said write data is then written in said first memory cell by applying said high voltage, second means responsive to said operation end signal for causing said first means to terminate said data write process, third means responsive to said data read request issued while said first means is applying said high voltage to said first memory cell in said data write process, for commanding said first means to stop applying said high voltage to said first memory cell to suspend said data write process, for reading out data from a second memory cell of said nonvolatile memory designated by said read address and thereafter for allowing said first means to reapply said high voltage to resume the suspended data write process and fourth means for commanding said timer means to suspend said time-counting operation in response to said data read request issued while said first means is applying said high voltage to said first memory cell in said data write process and for allowing said timer means to resume said time-counting operation after said third means reads out data from said second memory cell, said timer means thereby delaying the generation of said operation end signal.

2. The microcomputer as claimed in claim 1, wherein said microcomputer further comprises a terminal supplied with a power voltage and said first means includes booster means for boosting, when activated, said power voltage and for generating said high voltage after a predetermined period of time, said booster means being deactivated when said first means is commanded to suspend said data write process and being reactivated when said first means is allowed to resume said suspended data write process, and said further means continuing to command said timer means to suspend said time-counting operation until said booster means generates said high voltage based upon the reactivation thereof even after said third means reads out data from said second memory cell.

3. An electrically erasable and programmable nonvolatile memory for a microcomputer issuing a data write request and a data read request to said memory, said data write request including a write address and said data read request including a read address, said memory comprising a memory cell array, timer means for carrying out a time-counting operation to generate an end signal when a predetermined time elapses, performing means responsive to said data write request for performing a data writing operation by keeping a high voltage applied to a first memory cell designated by said write address until said timer means generates said end signal, means responsive to said data read request issued while said high voltage is being applied to said first memory cell in said data writing operation for commanding said performing means to stop applying said high voltage to suspend said data writing operation irrespective of said timer means not generating said end signal, means for reading out data from a second memory cell designated by said read address while said performing means is suspending said data write operation, means for allowing said performing means to reapply said high voltage to resume the suspended data writing operation after said data is read out from said second memory cell, and means for commanding said timer means to suspend said time-counting operation operation in response to said read data request issued while said high voltage is being applied to said first memory cell in said data writing operation and for allowing said timer means to resume the suspended time-counting operation after said data is read out from said second memory cell, said timer means thereby delaying generation of said end signal.

4. A method of reading and writing data from and into an electrically erasable programmable nonvolatile memory, comprising the steps of:

performing, in response to a data write request including a write address and write data, a time-counting operation to generate a first end signal after a first period of time and further to generate a second end signal after a second period of time from the generation of said first end signal;

selecting, in response to said data write request, a first memory cell of said nonvolatile memory designated by said write address;

applying a high voltage continuously to said first memory cell until said first end signal is generated to erase data stored in said first memory cell and thereafter applying said high voltage again continuously to said first memory cell until said second end signal is generated to write said write data into said first memory cell;

suspending, in response to a data read request including a read address, application of said high voltage to said first memory cell even upon non-receipt of a corresponding one of said first and second end signals;

suspending, in response to said read request, said time-counting operation to delay the generation of said corresponding one of said first and second end signals;

selecting a second memory cell of said nonvolatile memory, designated by said read address while application of said high voltage is being suspended;

reading out data from said second memory cell;

resuming said time-counting operation after said data is read out from said second memory cell; and

resuming applying said high voltage to said first memory cell after said data is read out from said second memory cell.

5. The method as claimed in claim 4, wherein said method further comprises the step of boosting a power voltage supplied to said nonvolatile memory to generate said high voltage, and said step of resuming said time-counting operation resumes said time-counting operation after said data is read out from said second memory cell and said high voltage is generated.