External procedure invocation apparatus utilizing internal branch vector interrupts and vector address generation, in a RISC chip

• US 5,287,522 A
• Filed: 06/29/1990
• Issued: 02/15/1994
• Est. Priority Date: 06/29/1990
• Status: Expired due to Term

• Current Assignee: Bull HN Information Systems Incorporated (Atos SE)
• Original Assignee: Bull HN Information Systems Incorporated (Atos SE)
• Inventors: Brown, Richard P., Smith, Steven S., Joyce, Thomas F.
• Primary Examiner(s): Lee, Thomas C.
• Assistant Examiner(s): Von Buhr, Maria N.
• Application Number:
  US07/546,347
• Time in Patent Office: 1,327 Days
• Field of Search: 364/DIG. 1, 364/DIG. 2, 395/375, 395/425, 395/725
• US Class Current: 712/244
• CPC Class Codes: G06F 13/24 using interrupt G06F13/32 takes precedence
• CPC Class Codes: G06F 9/3861 Recovery, e.g. branch miss-prediction, exception handling error detection or correction G06F11/00
• CPC Class Codes: G06F 9/3879 for non-native instruction execution, e.g. executing a command; for Java instruction set

Abstract

A system includes first and second processing units which are interconnected by a bidirectional bus. The first processing unit is a microprocessor chip programmed for executing procedures stored in an on-chip instruction cache unit. The second processing unit receives requests from an external source such as a system bus. The microprocessor chip includes a branch vector facility which connects to the bus. The second processing unit in response to an external request, generates a vector branch address. The processing unit transfers the vector branch address to the branch vector facility for storage along with setting a write indicator. The microprocessor chip, upon detecting that the write indicator was set, branches to the procedure specified by the branch vector address for executing the instructions of the procedure to carry out those operations required for processing the external request or event.

Claims

1. A system for processing requests received from a system bus, said system comprising:

an interface chip including vector address generation means coupled to said system bus for receiving requests, said vector address generation means in response to a predetermined type of request generating a branch vector address;

a microprocessor chip including;

an instruction cache for storing instructions including branch vector instructions, of a number of procedures fetched from said system bus as required for executing processing operations for handling the requests;

a branch vector register for storing said branch vector address;

a read indicator and a write indicator associated with said register;

bidirectional bus interconnecting said interface chip address generation means and microprocessor chip register and read/write indicators the read indicator and the write indicator for transferring of information between said chips using a standard protocol; and

,

said microprocessor chip further including instruction decode and control means operatively coupled to said branch vector register and to said read indicator and said write indicator said microprocessor instruction decode and control means upon detecting a branch vector instruction in a procedure under execution specifying said vector register as a source of a branch address, being operative to test said write indicator for causing said microprocessor chip to branch to one of said number of procedures specified by said branch vector address when said write indicator is in an active state for processing said predetermined type of request and said microprocessor chip switching said read indicator to an active state upon having processed the request signaling said interface chip through said bidirectional bus that said interface chip can transfer to a new vector address through said bidirectional bus for processing another predetermined type of request.

2. The system of claim 1 wherein execution of said branch vector instruction causes said microprocessor chip to poll for system bus request by testing said write indicator said microprocessor chip in an absence of said write indicator being set to said active state, continues executing instructions of said procedure until a next branch vector instruction is fetched.

3. The system of claim 1 wherein each of said plurality number of procedures include a number of reduced instruction set (RISC) type of instructions and wherein said branch vector instruction is a RISC type of instruction.

4. The system of claim 1 wherein said instruction cache is located on said microprocessor chip and said microprocessor chip is a RISC type chip.

5. The system of claim 1 wherein said address generator generation means of said interface chip includes a control sequencer and an address generator circuit, said control sequencer being connected to said bidirectional bus and to said system bus and said address generator circuit being connected to said control sequencer and to said bidirectional bus, said control sequencer in response to said predetermined type of request causing said address generator circuit to generate and transfer said branch vector address to said microprocessor chip through said bidirectional bus when said read indicator is in said active state.

6. A system for processing requests or events received from a system bus, said system comprising:

an interface chip including vector address generation means coupled to said system bus for receiving requests, said address generation means in response to a predetermined type of request generating an interrupt signal indicative of an interrupt condition and a branch vector address;

a microprocessor chip including;

an instruction cache for storing instructions including branch vector instructions, of a number of procedures fetched from said system bus as required for executing processing operations for handling the requests;

a branch vector register for storing said branch vector address;

a read indicator and a write indicator associated with said register;

bidirectional bus interconnecting said interface chip address generation means and microprocessor chip register and the read indicator and the write indicator for transferring of information between said chips using a standard protocol; and

,

said microprocessor chip further including instruction decode and control means operatively coupled to said register and to said read indicator and said write indicator said instruction decode and control means further including interrupt processing means connected to said system bus for receiving said interrupt signal from said interface chip, said instruction decode and control means upon detecting an interrupt condition, testing said write indicator and causing said microprocessor chip to branch to one of said number of procedures specified by said branch vector address for servicing said interrupt condition when said write indicator is in an active state, said microprocessor chip switching said read indicator to an active state upon having processed said predetermined type of request signaling said interface chip through said bidirectional bus that said interface chip can transfer a new branch vector interrupt address through said bidirectional bus for processing another predetermined type of request.

7. The system of claim 6 wherein said branch vector interrupt address used to process said interrupt condition is coded to include information specifying the type and priority level of said interrupt condition for causing said branch to one of a number of handlers specially designed to handle the interrupt condition so as to reduce overhead.

8. The system of claim 6 wherein each of said number of procedures include a number of reduced instruction set (RISC) type of instructions.

9. The system of claim 6 wherein said instruction cache is located on said microprocessor chip and said microprocessor chip is a RISC type chip.

10. The system of claim 6 wherein said address generator means of said interface chip includes a control sequencer and an address generator circuit, said control sequencer being connected to said bidirectional bus and to said system bus for transferring said interrupt signal and receiving said requests, respectively, and said address generator circuit being connected to said control sequencer and to said bidirectional bus, said control sequencer in response to said predetermined type of request causing said address generator circuit to generate and transfer said branch vector interrupt address to said interrupt signal to said microprocessor chip through said bidirectional bus when said read indicator is in said active state.

11. A method of organizing a system including a microprocessor chip for operating under the control of external invocation apparatus, said method comprising the steps of:

(a) including a branch vector register and associated read indicator and write indicator within said microprocessor chip for storing a branch vector address and read/write indications;

(b) including vector address generation means within an interface chip and coupling said vector address generation means to a system bus for receiving requests to be processed by said microprocessor chip through a number of procedures, one or more of said number of procedures having a branch vector instruction;

(c) connecting a bidirectional bus to said branch vector register and associated said associated read indicator and write indicator within said microprocessor chip and to said vector address generation means within said interface chip for transferring information therebetween through a standard protocol;

(d) connecting said vector address generation means to said system bus for generating said branch vector address in response to a request from said system bus to be transferred to said vector register; and

,

(e) connecting said microprocessor chip to said write indicator for testing and to enable a branch to a procedure for processing said request which is specified by said vector address transferred to said branch vector register each time a branch vector instruction is fetched from one of said number of procedures and executed by said microprocessor chip when said write indicator is in an active state.

12. The method of claim 11 wherein said method further includes the steps of:

(f) connecting said microprocessor chip to said read indicator for setting said read indicator to an active state for signaling said interface chip that said vector register has been accessed by said microprocessor chip for enabling transfer of a next vector address by said interface chip for processing another request.

13. A method of organizing a system including a microprocessor chip for operating said microprocessor chip under the control of external invocation apparatus, said method comprising the steps of:

(a) including within the microprocessor chip, a branch vector register for storing a branch vector interrupt address and associated read indicator and write indicator;

(b) including within an interface chip, vector address generation means and coupling said generation means to a system bus for receiving requests;

(c) connecting a bidirectional bus to said branch vector register and said associated read indicator and write indicator of said microprocessor chip and to said vector address generation means of said interface chip for transferring information therebetween through a standard protocol;

(d) connecting said generation means to transfer on said bidirectional bus to said vector register, each branch vector interrupt address generated by said generation means in response to a request from said system bus requiring interrupt processing;

(e) connecting said interface chip for setting an interrupt within said microprocessor chip through said bidirectional bus; and

,

(f) connecting said microprocessor chip for branching to a procedure specified by the branch vector interrupt address each time said interrupt is acted on when said write indicator is in an active state, to execute instructions of a handler routine for processing said request.

14. The method of claim 13 wherein said method further includes the step of:

(g) said microprocessor chip setting said read indicator to an active state for signaling said interface chip that said vector register has been accessed for enabling transfer of a new vector interrupt address by said interface chip for processing another request.