Software controlled power shutdown in an integrated circuit

• US 5,287,525 A
• Filed: 01/28/1993
• Issued: 02/15/1994
• Est. Priority Date: 11/29/1989
• Status: Expired due to Term

• Current Assignee: Analog Devices International Unlimited Company (Analog Devices, Inc.)
• Original Assignee: Linear Technology Corporation (Analog Devices, Inc.)
• Inventors: Rempfer, William C., Lum, Sammy S.
• Primary Examiner(s): Ray, Gopal C.
• Application Number:
  US08/010,477
• Time in Patent Office: 383 Days
• Field of Search: 395/750, 395/575, 364/707, 365/226, 365/227, 371/66
• US Class Current: 713/300
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3246 by software initiated power-off

Abstract

Power shutdown of an integrated circuit such as a data acquisition system is implemented by software command. In one embodiment of a data acquisition system, an 8 bit data input word for configuring the operation of the data acquisition system includes two word length bits which define the length of data output words. One combination of the word length bits is utilized to command power shutdown. A decoder within the integrated circuit identifies the power shutdown command and generates a power shutdown signal (PS) to minimize power consumption when the circuit is not in operation.

Claims

1. A method for providing an internal power shutdown signal in an integrated circuit in response to a multi-bit circuit configuration word received by said integrated circuit, said integrated circuit being enabled to receive said configuration word upon receipt of a chip select signal, wherein said circuit configuration work includes at least one configuration bit used by said integrated circuit to configure said integrated circuit for operation, said method comprising the steps of:

(a) serially clocking said circuit configuration word into said integrated circuit, said circuit configuration word including at least one word length bit for defining lengths of output words produced by said integrated circuit;

(b) decoding said at least one configuration bit of said circuit configuration word into a first data value and configuring said integrated circuit into an operative mode in accordance with said first data value and said chip select signal;

(c) decoding said at least one word length bit of said configuration word into a second data value and comparing said second data value with a predefined value representative of a power shutdown command;

(d) generating a power shutdown signal on the basis of said comparison of said second data value with said predefined power shutdown command, said power shutdown signal being reset by the chip select signal received by said integrated circuit; and

(e) shutting down power in response to generation of said power shutdown signal.

2. The method as defined by claim 1 wherein said integrated circuit is a data acquisition system, said circuit configuration word is an 8 bit input data word.

3. An apparatus for providing an internal signal for power shutdown in an integrated circuit which receives a multi-bit circuit configuration word, said integrated circuit being enabled to receive said configuration word upon receipt of a chip select signal, wherein said circuit configuration word includes at least one configuration bit used by said integrated circuit to configure said integrated circuit for operation, comprising:

means for clocking said circuit configuration word into said integrated circuit, said circuit configuration word including at least one word length bit for defining lengths of output words produced by said integrated circuit;

means for decoding said at least one configuration bit and said at least one word length bit of said circuit configuration word into first and second data values, respectively, and for comparing said second data value with a predefined value representative of a power shutdown command;

means for configuring said integrated circuit into an operative mode in accordance with said first data value and said chip select signal; and

means for generating a power shutdown signal for said integrated circuit on the basis of said comparison of said second data value with said predefined value representative of a power shutdown command wherein said power shutdown signal is reset by the chip select signal received by said decoding means.

4. Apparatus as defined by claim 3 wherein said integrated circuit is a data acquisition system.