Logical signal output drivers for integrated circuit interconnection

• US 5,287,527 A
• Filed: 12/28/1992
• Issued: 02/15/1994
• Est. Priority Date: 12/28/1992
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Schuelke, Brian A., Delp, Gary S.
• Primary Examiner(s): LaRoche, Eugene R.
• Assistant Examiner(s): MAI, SON LUU
• Application Number:
  US07/997,380
• Time in Patent Office: 414 Days
• Field of Search: 365/230.01, 365/189.05, 365/230.06, 365/230.08, 365/230.03, 365/230.04, 365/206, 307/443, 307/451, 307/270, 307/469, 395/400, 395/425
• US Class Current: 365/230.01
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

Disclosed is a logic output signal generating integrated circuit having a plurality of output drivers connected in parallel between a power bus and a ground bus. Each output driver has a pull up device disposed between the power bus and an output terminal and a pull down device disposed between the output terminal and the ground bus. Output drivers are paired for the reception of control signals. Control gates to the pull up device and the pull down device for one output driver in a pair is connected to receive an on-chip logic signal. The second output driver of the pair has the complement of that logic signal applied to the control gates of its pull up and pull down devices. An inverter operates on the logic signal to provide the complement. The load is divided between the output drivers for the true signals and those for the complementary signals.

Claims

1. A memory storage device comprising:

first and second banks of integrated circuit storage devices;

an address signal generator for providing an address and a complement of the address;

a first logic bus connected between the address signal generator and the first bank of integrated storage devices for for applying the address to the first bank;

a second logic bus connected between the address signal generator and the second bank of integrated storage devices for applying the complement of the address to the second bank; and

a data bus for accessing a location in the first bank in response to application of the address and a location in the second bank in response to application of the complement of the address to read or write a dataword divided between the locations.

2. A memory storage device as set forth in claim 1, and further comprising:

an output driver on the address generator connected to each line in the first logic bus and the second logic bus; and

wherein output drivers connected to lines in the first logic bus receive on chip address signals and output drivers connected to lines in the second logic bus receive inverted on chip address signals.

3. A memory storage device as set forth in claim 1, wherein the address signal generator is an integrated circuit and includes:

a plurality of terminals for receiving on chip address signals;

a plurality of inverters connected to the terminals for generating inverted on chip address signals;

a power bus and a ground bus; and

a plurality of output driver circuits connected in parallel between the power bus and the ground bus with each output driver circuit having an output terminal connected to a line from the first address bus or the second address bus and a control input connected to one of the input terminals or to one of the plurality of inverters.

4. A memory storage device as set forth in claim 3, wherein each output driver further comprises:

a pull up device connected between the power bus and the output terminal; and

a pull down device connected between the output terminal and the ground bus.

5. A memory storage device as set forth in claim 4, wherein the pull up and pull down devices are complementary metallic oxide semiconductor field effect transistors.

6. A data processing system comprising:

a central processing unit;

a system data bus connected to central processing unit;

a system address bus connected to central processing unit; and

first and second banks of integrated circuit storage devices;

address signal processing logic connected between the system address bus and the first and second banks of integrated storage devices to apply an address over a first logic bus to the first bank of integrated storage devices and a complement of the address over a second logic bus to the second bank of integrated storage devices; and

the system data bus accessing a location in the first bank in response to application of the address thereto and a location in the second bank in response to application of the complement of the address thereto to read or write a data word.

7. A data processing system as set forth in claim 6, and further comprising:

an output driver for each line in the first logic bus and the second logic bus;

wherein the output drivers connected to lines in the first logic bus receive on chip address signals and output drivers connected to lines in the second logic bus receive inverted on chip address signals.

8. A data processing system as set forth in claim 7, wherein the address signal processing logic further includes:

a plurality of terminals for receiving on chip address signals;

a plurality of inverters connected to the terminals for generating inverted on chip address signals;

a power bus and a ground bus; and

a plurality of output driver circuits connected in parallel between the power bus and the ground bus with each output driver circuit having an output terminal connected to a line from the first address bus or the second address bus and a control input connected to one of the input terminals or to one of the plurality of inverters.

9. A data processing system as set forth in claim 8, wherein each output driver further comprises:

a pull up device connected between the power bus and the output terminal; and

a pull down device connected between the output terminal and the ground bus.

10. A data processing system as set forth in claim 9, wherein the pull up and pull down devices are complementary metallic oxide semiconductor field effect transistors.

11. A memory storage device comprising:

first and second banks of integrated circuit storage;

an address signal generator;

a first logic bus connected to the first bank of integrated circuit storage;

a second logic bus connected to the second bank of integrated circuit storage;

a power bus and a ground bus;

a plurality of output driver circuits connected in parallel between the power bus and the ground bus with each output driver circuit having an output terminal connected to a line from the first logic bus or the second logic bus and a control input connected to one of the input terminals or to one of the plurality of inverters.

12. A memory storage device as set forth in claim 11, wherein each output driver further comprises:

a pull up device connected between the power bus and the output terminal; and

a pull down device connected between the output terminal and the ground bus.

13. A memory storage device as set forth in claim 12, wherein the pull up and pull down devices are complementary metallic oxide semiconductor field effect transistors.