Digital ECL bipolar logic gates suitable for low-voltage operation

• US 5,289,055 A
• Filed: 11/17/1992
• Issued: 02/22/1994
• Est. Priority Date: 11/17/1992
• Status: Expired due to Term

• Current Assignee: American Telephone & Telegraph Company (AT&T, Inc.)
• Original Assignee: AT&T, Inc.
• Inventors: Razavi, Behzad
• Primary Examiner(s): Westin, Edward P.
• Assistant Examiner(s): ROSEEN, RICHARD R
• Application Number:
  US07/977,342
• Time in Patent Office: 462 Days
• Field of Search: 307/455, 307/289, 307/471, 307/272.2, 307/480
• US Class Current: 326/126
• CPC Class Codes: H03K 19/086 Emitter coupled logic

Abstract

Several digital bipolar logic circuits are described, for applications as digital logic gates and for buffering and level-shifting. These circuits are adapted for high-speed operation, and they have reduced supply-voltage requirements. In each of these circuits, a control device such as a transistor turns an input circuit on or off by means of an emitter-to-emitter connection. However, unlike most conventional ECL circuits, these circuits avoid stacked transistor configurations.

Claims

1. A digital circuit for producing an output voltage responsive to A, B, and C input signals and their respective complements A, B, and C, the circuit comprising:

a) first and second bipolar transistors, each having a base, an emitter, and a collector, the transistors constituting a first differential pair and having emitter terminals electrically connected to a first common node;

b) means for inputting the A signal to the first transistor base and means for inputting the A signal to the second transistor base;

c) third and fourth bipolar transistors, each having a base, an emitter, and a collector, the transistors constituting a second differential pair and having emitter terminals electrically connected to a second common node;

d) means for inputting the B signal to the third transistor base and means for inputting the B signal to the fourth transistor base;

e) resistive means for electrically connecting a terminal which is maintained at a power supply voltage to the first and second nodes during at least a portion of the time that the circuit is operating;

f) resistive means for electrically connecting the collectors of the first, second, third, and fourth transistors to a terminal or group of terminals maintained at ground potential;

g) means, responsive to the C signal, for alternating the voltage at the first node between two distinct voltage levels such that when the node voltage is at one of the levels, the first and second transistors are disabled, and when the node voltage is at the other level, the first and second transistors are enabled;

h) means, responsive to the C signal, for alternating the voltage at the second node between two distinct voltage levels such that when the node voltage is at one of the levels, the third and fourth transistors are disabled, and when the node voltage is at the other level, the third and fourth transistors are enabled; and

i) first and second output voltage terminals, the first output terminal electrically connected to the collectors of the first and third transistors, and the second output terminal electrically connected to the collectors of the second and fourth transistors, CHARACTERIZED IN THAT

j) the alternating means comprise fifth and sixth bipolar transistors, each having a base and an emitter, and further having a collector electrically connected to a terminal maintained at ground potential;

k) the emitter of the fifth transistor is electrically connected to the first node, and the emitter of the sixth transistor is electrically connected to the second node;

l) the alternating means further comprise means for electrically inputting the C signal to the base of the fifth transistor and for inputting the C signal to the base of the sixth transistor such that the voltages at the first and second nodes change in a complementary fashion in response to changes in the C signal; and

m) no path for electric current between the power supply voltage terminal and a terminal at ground potential via any one of the first, second, third, and fourth transistors includes a stacked pair of transistors.

2. The circuit of claim 1, wherein the C signal is a clock signal and the output voltage corresponds, in alternation, to the A signal or the B signal according to alternations of the clock signal, resulting in a multiplexed output.

3. The circuit of claim 1, wherein the B signal is the logical equivalent of the A signal, such that the output voltage corresponds to the exclusive OR function A ⊕

C.

4. A digital latch circuit for producing an output voltage which corresponds to the voltage state of an input signal at a time selected by changing the voltage state of a clock signal, the circuit comprising:

a) first and second bipolar transistors, each having a base, an emitter, and a collector, the transistors constituting a differential pair and having emitter terminals electrically connected to a first common node;

b) means for inputting the input signal to the first transistor base and means for inputting the input signal complement to the second transistor base;

c) third and fourth bipolar transistors, each having a base, an emitter, and a collector, the transistors constituting a latch pair wherein the base of each is electrically connected to the collector of the other, said third and fourth transistors having emitter terminals electrically connected to a second common node;

d) resistive means for electrically connecting a terminal which is maintained at a power supply voltage to the first and second nodes during at least a portion of the time that the circuit is operating;

e) resistive means for electrically connecting the collectors of the first, second, third, and fourth transistors to a terminal or group of terminals maintained at ground potential;

f) means, responsive to the clock signal, for alternating the voltage at the first node between two distinct voltage levels such that when the node voltage is at one of the levels, the first and second transistors are disabled, and when the node voltage is at the other level, the first and second transistors are enabled;

g) means, responsive to the clock signal complement, for alternating the voltage at the second node between two distinct voltage levels such that when the node voltage is at one of the levels, the third and fourth transistors are disabled, and when the node voltage is at the other level, the third and fourth transistors are enabled; and

h) first and second output voltage terminals, the first output terminal electrically connected to the collectors of the first and third transistors, and the second output terminal electrically connected to the collectors of the second and fourth transistors, CHARACTERIZED IN THAT

i) the alternating means comprise fifth and sixth bipolar transistors, each having a base and an emitter, and further having a collector electrically connected to a terminal maintained at ground potential;

j) the emitter of the fifth transistor is electrically connected to the first node, and the emitter of the sixth transistor is electrically connected to the second node;

k) the alternating means further comprise means for electrically inputting the clock signal to the base of the fifth transistor and for inputting the clock signal complement to the base of the sixth transistor such that the voltages at the first and second nodes change in a complementary fashion in response to changes in the clock signal; and

l) no path for electric current between the power supply voltage terminal and a terminal at ground potential via any one of the first, second, third, and fourth transistors includes a stacked pair of transistors.

5. A digital circuit, responsive to an A input signal, a B input signal, and the complementary A and B signals, for producing, at a first node, an output voltage representing the exclusive OR function A⊕

B, the circuit comprising;

a) at least one terminal maintained at ground potential and at least one terminal maintained at a power supply voltage;

b) first and second bipolar transistors, to be referred to as the first and second gate transistors, said gate transistors providing alternate paths for electric current flowing between the power supply and ground terminals, each of said gate transistors having an emitter, a base, and a collector, the collector of said gate transistors electrically connected at the first node;

c) resistive means electrically connected to the ground terminal and to the first node such that electric current flowing through either one of the alternate paths produces a voltage drop across said resistive means, said voltage drop being measurable as the output voltage;

d) first means, responsive to the A and B signals, for controlling the flow of electric current through the first gate transistor such that a substantial flow of current is permitted only when the A and B signals both have high voltage states; and

e) second means, responsive to the complementary A and B signals, for controlling the flow of electric current through the second gate transistor such that a substantial flow of current is permitted only when the complementary A and B signals both have high voltage states, CHARACTERIZED IN THAT

f) the first controlling means comprise first and second bipolar transistors, to be referred to as the first and second control transistors, each of said control transistors having a collector electrically connected to a ground terminal and an emitter electrically connected to the emitter of the first gate transistor, and further having a base;

g) the second controlling means comprise third and fourth bipolar transistors, to be referred to as the third and fourth control transistor, each of said control transistors having a collector electrically connected to a ground terminal and an emitter electrically connected to the emitter of the second gate transistor, and further having a base;

h) the circuit further comprises means for inputting the A signal to the base of the first control transistor, the B signal to the base of the second control transistor, the complementary B signal to the base of the third control transistor, and the complementary A signal to the base of the fourth control transistor;

i) a common-mode voltage level is associated with the A and B signals, and the circuit further comprises means for applying a bias voltage to the bases of the first and second gate transistors, the bias voltage approximately equal to the common-mode voltage; and

j) neither of the alternate paths includes a stacked pair of transistors.

6. The circuit of claim 5, further comprising a level-shifting resistor, wherein:

a) the first resistive means and the collectors of the first, second, third and fourth bipolar transistors are electrically connected to a ground terminal through the level-shifting resistor; and

b) the resistance of the level-shifting resistor is selected such that the common-mode level of the output voltage is shifted by a predetermined amount relative to the output-voltage common-mode level of an otherwise equivalent circuit having a level-shifting resistance of zero.

7. The circuit of claim 5, further comprising an XNOR circuit responsive to the A and B input signals and the complementary A and B input signals, the XNOR circuit adapted to produce, at a second node, an XNOR output voltage that represents the logical complement of the output voltage at the first node, such that the voltage difference between the first and second nodes constitutes a differential output signal, wherein the XNOR circuit comprises:

a) third and fourth bipolar, gate transistors for providing alternate paths for electric current flowing between the power supply and ground terminals, each of said gate transistors having a collector, the collectors of said gate transistors electrically connected at the second node;

b) resistive means electrically connected to the ground terminal and to the second node such that electric current flowing through either one of the alternate paths produces a voltage drop across said resistive means, said voltage drop being measurable as the XNOR output voltage;

c) fifth and sixth bipolar, control transistors for controlling the flow of electric current through the third gate transistor such that a substantial flow of current is permitted only when the A signal has a low voltage state and the B signal has a high voltage state; and

d) seventh and eigth bipolar, control transistors for controlling the flow of electric current through the fourth gate transistor such that a substantial flow of current is permitted only when the A signal has a high voltage state and the B signal has a low voltage state.

8. A digital circuit for providing an output voltage which corresponds to an input signal, the circuit comprising:

a) at least one terminal maintained at ground potential, and at least one terminal maintained at a power supply voltage level;

b) two bipolar transistors, to be referred to as the first and second input transistors, each having a base, an emitter, and a collector;

means for applying the input signal to the base of the first input transistor; and

means for applying the input signal complement to the base of the second input transistor;

c) two bipolar transistors, to be referred to as the first and second output transistors, each having a base, an emitter, and a collector;

d) first resistive means for electrically coupling the collectors of the first and second output transistors to a ground terminal or terminals such that electric current flowing into the collector of each output transistor will establish a voltage drop, one or both of said voltage drops defining the output voltage;

e) means for applying a bias voltage to the bases of the output transistors;

f) second resistive means for electrically connecting the emitters of the input transistors to a terminal or terminals at the power supply voltage; and

g) means for electrically connecting the first and second input transistors to the first and second output transistors, respectively, such that the electric current flowing into the collector of each output transistor can be modulated by the input signal or input signal complement applied to the base of the corresponding input transistor, CHARACTERIZED IN THAT

h) the emitter of each input transistor is electrically connected to the emitter of the corresponding output transistor;

i) the biasing means comprise a voltage divider having a first end electrically connected to the emitter of the first output transistor, a second end electrically connected to the emitter of the second output transistor, and a tap intermediate the first and second ends;

j) the biasing means further comprise a bipolar transistor, to be referred to as the bias transistor, said bias transistor having an emitter, a base, and a collector, said collector being electrically connected to said base such that said bias transistor is self-biased;

k) the emitter of the bias transistor is electrically connected to the tap, the base of the bias transistor is electrically connected to the bases of the first and second output transistors, and the collector of the bias transistor is electrically connected through third resistive means to a ground terminal; and

l) no path for electric current between a power supply voltage terminal and a ground terminal via any one of the input or output transistors includes a stacked pair of transistors.