Video processing circuit with line memory control

• US 5,289,284 A
• Filed: 11/12/1992
• Issued: 02/22/1994
• Est. Priority Date: 06/01/1990
• Status: Expired due to Term

• Current Assignee: Thomson Consumer Electronics Incorporated (Vantiva SA)
• Original Assignee: Thomson Consumer Electronics Incorporated (Vantiva SA)
• Inventors: Saeger, Timothy W., Ersoz, Nathaniel H.
• Primary Examiner(s): Groody, James J.
• Assistant Examiner(s): Burgess, Glenton B.
• Application Number:
  US07/691,031
• Time in Patent Office: 467 Days
• Field of Search: 358/160, 358/140, 358/180, 358/148, 358/183, 358/133, 358/22, 358/141, 358/182, 358/11
• US Class Current: 348/561
• CPC Class Codes: G06T 3/04 Context-preserving transformations, e.g. by using an importance map panospheric to cylindrical image transformations G06T3/12
• CPC Class Codes: G06T 3/4007 based on interpolation, e.g. bilinear interpolation image demosaicing G06T3/4015; edge-driven or edge-based scaling G06T3/403
• CPC Class Codes: H04N 19/90 using coding techniques not provided for in groups H04N19/10-H04N19/85, e.g. fractals
• CPC Class Codes: H04N 3/223 Controlling dimensions by maintaining the cathode-ray tube high voltage constant H04N3/185
• CPC Class Codes: H04N 3/227 Centering
• CPC Class Codes: H04N 3/27 Circuits special to multi-standard receivers
• CPC Class Codes: H04N 5/2624 for obtaining an image which is composed of whole input images, e.g. splitscreen
• CPC Class Codes: H04N 5/45 Picture in picture , e.g. displaying simultaneously another television channel in a region of the screen
• CPC Class Codes: H04N 7/007 Systems with supplementary picture signal insertion during a portion of the active part of a television signal, e.g. during top and bottom lines in a HDTV letter-box system
• CPC Class Codes: H04N 7/01 Conversion of standards , e.g. involving analogue television standards or digital television standards processed at pixel level
• CPC Class Codes: H04N 7/0105 using a storage device with different write and read speed
• CPC Class Codes: H04N 7/0122 the input and the output signals having different aspect ratios
• CPC Class Codes: H04N 7/015 High-definition television systems
• CPC Class Codes: H04N 9/64 Circuits for processing colour signals H04N9/77 takes precedence; camera processing pipelines for processing colour signals H04N23/84
• CPC Class Codes: H04N 9/641 Multi-purpose receivers, e.g. for auxiliary information H04N9/642 takes precedence

Abstract

A line memory and control system comprises a line memory, for example a first in first out (FIFO) device. A comparator compares a first value, specifying a location in the horizontal line period where reading or writing of the line memory is to begin, with a second value, fixing pixel location within each line period. A register stores the number of data samples stored in the line memory. A counter counts the number of data samples which have actually been written into the line memory or read from the line memory. The counter has an output of the comparator as a first input and the number of data samples previously stored in the line memory as a second input. In the case of both compression and expansion, a line memory control system assures that the number of samples written into each FIFO line memory be the same as the number of samples read out of each FIFO line memory.

Claims

1. A video signal processing circuit, comprising:

a line memory for said video signal;

means for writing and reading of video data samples into and out of said line memory, different numbers of data samples per line being stored during expansion and compression of said video signal;

means for comparing a first value, specifying a first pixel location in the horizontal line period where reading or writing of said line memory is to begin, with a second value specifying a second pixel location within each line period;

means for storing a third value corresponding to the number of data samples stored in said line memory; and

,

means for counting the number of data samples which have actually been written into said line memory or read from said line memory, said counting means having an output of said comparing means as a first input and said third value as a second input.

2. The circuit of claim 1, further comprising means for smoothing data compressed or expanded in said line memory.

3. The circuit of claim 1, wherein said line memory is a first in first out (FIFO) device having independently enabled write and read ports.

4. A controller for a line memory in a video signal processing circuit, the controller comprising:

means for writing and reading of video data samples into and out of said line memory, different numbers of data samples per line being stored during expansion and compression of said video signal;

means for comparing a first value, specifying a first pixel location in the horizontal line period where reading or writing of said line memory is to begin, with a second value specifying a second pixel location within each line period;

means for storing a third value corresponding to the number of data samples stored in said line memory; and

,

means for counting the number of data samples which have actually been written into said line memory or read from said line memory, said counting means having an output of said comparing means as a first input and said third value as a second input.

5. The controller of claim 4, further comprising means for smoothing data compressed or expanded in said line memory.

6. The circuit of claim 4, wherein said line memory is a first in first out (FIFO) device having independently enabled write and read ports.