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Echo canceller using impulse response estimating method

  • US 5,289,539 A
  • Filed: 09/12/1991
  • Issued: 02/22/1994
  • Est. Priority Date: 09/12/1990
  • Status: Expired due to Fees
First Claim
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1. An echo canceller using an FIR filter for removing an echo from at transmission input signal, the echo resulting from a reflection of a received signal through an echo path, comprising:

  • a first memory for storing N latest samples of the received signal;

    a second memory for storing an N-th order impulse response of the echo path;

    a first delay circuit for delaying the received signal by M samples;

    a third memory for storing N samples of an output of said first delay circuit;

    a second delay circuit for delaying the transmission input signal by M samples;

    a first convolution circuit for multiplying and adding the outputs of said first and second memories;

    a second convolution circuit for multiplying and adding the outputs of said second and third memories;

    a first subtractor for subtracting the output of said first convolution circuit from the transmission input signal to produce a transmission output signal;

    a second subtractor for subtracting the output of said second convolution circuit from the output of said second delay circuit;

    a first correction amount calculating circuit for determining a first correction amount on the basis of the transmission output signal from said first subtractor and said received signal;

    a first multiplier for multiplying said first correction amount by the output of said first memory;

    `a first adder for adding the output of said first multiplier to the impulse response from said second memory;

    a second correction amount calculating circuit for determining a second correction amount on the basis of the output of said second subtractor and the output of said first delay circuit;

    a second multiplier for multiplying said second correction amount by the output of said third memory; and

    a second adder for adding the output of said second multiplier to the output of said first adder and feeding back the resulting sum to said second memory.

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