Semiconductor device and method of fabricating semiconductor device
First Claim
1. A semiconductor device comprising:
- (a) a metal base plate,(b) a composite substrate mounted on said metal base plate,said composite substrate including;
(b-1) a first ceramic substrate joined onto said metal base plate,(b-2) a first metal plate joined to an upper surface of said first ceramic substrate and formed into a predetermined pattern, said first metal plate having first and second regions arranged parallel to the upper surface of said first ceramic substrate,(b-3) a second ceramic substrate joined to an upper surface of said first region of said first metal plate, and(b-4) a second metal plate joined to an upper surface of said second ceramic substrate and formed into a predetermined pattern,said semiconductor device further comprising;
(c) a power semiconductor device mounted on an upper surface of said second region of said first metal plate, and(d) a control semiconductor device mounted on an upper surface of said second metal plate for controlling said power semiconductor device,at least said second region of said first metal plate including;
(b-3-1) a first metal layer joined to the upper surface of said first ceramic substrate,(b-3-2) a second metal layer bonded onto said first metal layer, and(b-3-3) a third metal layer bonded onto said second metal layer,said second metal layer being lower in coefficient of thermal expansion than said first and third metal layers,said first region of said first metal plate being an electrode layer to be held at a constant potential.
1 Assignment
0 Petitions
Accused Products
Abstract
A patterned first metal plate (310)is joined to an upper surface of a first ceramic substrate (301), and a second metal plate (330) is joined to an emitter electrode (310E) of the first metal plate (310) through a second ceramic substrate (320). Power devices (4) are mounted on a collector electrode (310C) of the first metal plate (310), and control devices (5) are mounted on the second metal plate (330). The emitter electrode (310E) of a metal layer lies between a high-voltage circuit having the first metal plate (310) and power devices (4) and a control (low-voltage) circuit having the control devices (5) and second metal plate (330). The emitter electrode (310E) serves as a shielding material, and the electrostatic shielding effect prevents noises applied to the high-voltage circuit from being led to the control circuit, so that the faulty operations of the control devices (5) are prevented and the reliability of the semiconductor device is improved.
-
Citations
20 Claims
-
1. A semiconductor device comprising:
-
(a) a metal base plate, (b) a composite substrate mounted on said metal base plate, said composite substrate including; (b-1) a first ceramic substrate joined onto said metal base plate, (b-2) a first metal plate joined to an upper surface of said first ceramic substrate and formed into a predetermined pattern, said first metal plate having first and second regions arranged parallel to the upper surface of said first ceramic substrate, (b-3) a second ceramic substrate joined to an upper surface of said first region of said first metal plate, and (b-4) a second metal plate joined to an upper surface of said second ceramic substrate and formed into a predetermined pattern, said semiconductor device further comprising; (c) a power semiconductor device mounted on an upper surface of said second region of said first metal plate, and (d) a control semiconductor device mounted on an upper surface of said second metal plate for controlling said power semiconductor device, at least said second region of said first metal plate including; (b-3-1) a first metal layer joined to the upper surface of said first ceramic substrate, (b-3-2) a second metal layer bonded onto said first metal layer, and (b-3-3) a third metal layer bonded onto said second metal layer, said second metal layer being lower in coefficient of thermal expansion than said first and third metal layers, said first region of said first metal plate being an electrode layer to be held at a constant potential. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
-
-
13. A semiconductor device, comprising:
-
(a) a metal base plate, (b) a composite substrate mounted on said metal base plate, said composite substrate including; (b-1) a first ceramic substrate joined onto said metal base plate, (b-2) a first metal plate joined to an upper surface of said first ceramic substrate and formed into a predetermined pattern, said first metal plate having first and second regions arranged parallel to the upper surface of said first ceramic substrate, (b-3) a second ceramic substrate joined to an upper surface of said first region of said first metal plate, and (b-4) a second metal plate joined to an upper surface of said second ceramic substrate and formed into a predetermined pattern, said semiconductor device further comprising; (c) a power semiconductor device mounted on an upper surface of said second region of said first metal plate, and (d) a control semiconductor device mounted on an upper surface of said second metal plate for controlling said power semiconductor device, at least said second region of said first metal plate including; (b-3-1) a first metal layer joined to the upper surface of said first ceramic substrate, (b-3-2) a second metal layer bonded onto said first metal layer, and (b-3-3) a third metal layer bonded onto said second metal layer, said second metal layer being lower in coefficient of thermal expansion than said first and third metal layers.
-
-
14. A composite substrate for use in a semiconductor device comprising:
-
(a) a first ceramic substrate, (b) a first metal plate joined to an upper surface of said first ceramic substrate and having first and second regions arranged parallel to the upper surface of said first ceramic substrate, (c) a second ceramic substrate joined onto said first region of said first metal plate, (d) a second metal plate joined to an upper surface of said second ceramic substrate, and (e) a third metal plate joined to a lower surface of said first ceramic substrate, at least said second region of said first metal plate including; (b-1) a first metal layer, (b-2) a second metal layer bonded onto said first metal layer, and (b-3) a third metal layer bonded onto said second metal layer, said second metal layer being lower in coefficient of thermal expansion than said first and third metal layers. - View Dependent Claims (15, 16, 17, 18, 19, 20)
-
Specification