Semiconductor device and method of fabricating semiconductor device

• US 5,291,065 A
• Filed: 12/14/1992
• Issued: 03/01/1994
• Est. Priority Date: 12/16/1991
• Status: Expired due to Fees

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Omachi, Hirofumi, Arai, Kiyoshi
• Primary Examiner(s): Clark, Sheila V.
• Application Number:
  US07/990,199
• Time in Patent Office: 442 Days
• Field of Search: 257/691, 257/692, 257/693, 257/700, 257/723, 257/724, 257/725, 257/728, 257/762, 257/763, 257/764, 257/770, 333/247
• US Class Current: 257/723
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/92247 the second connecting process involving a wire connector
• CPC Class Codes: H01L 23/5385 Assembly of a plurality of insulating substrates
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 23/60 Protection against electrostatic charges or discharges, e.g. Faraday shields
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 25/162 the devices being mounted on two or more different substrates
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01014 Silicon [Si]
• CPC Class Codes: H01L 2924/12041 LED
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/181 Encapsulation
• CPC Class Codes: H01L 2924/3025 Electromagnetic shielding

Abstract

A patterned first metal plate (310)is joined to an upper surface of a first ceramic substrate (301), and a second metal plate (330) is joined to an emitter electrode (310E) of the first metal plate (310) through a second ceramic substrate (320). Power devices (4) are mounted on a collector electrode (310C) of the first metal plate (310), and control devices (5) are mounted on the second metal plate (330). The emitter electrode (310E) of a metal layer lies between a high-voltage circuit having the first metal plate (310) and power devices (4) and a control (low-voltage) circuit having the control devices (5) and second metal plate (330). The emitter electrode (310E) serves as a shielding material, and the electrostatic shielding effect prevents noises applied to the high-voltage circuit from being led to the control circuit, so that the faulty operations of the control devices (5) are prevented and the reliability of the semiconductor device is improved.

Claims

1. A semiconductor device comprising:

(a) a metal base plate,

(b) a composite substrate mounted on said metal base plate,

said composite substrate including;

(b-1) a first ceramic substrate joined onto said metal base plate,

(b-2) a first metal plate joined to an upper surface of said first ceramic substrate and formed into a predetermined pattern, said first metal plate having first and second regions arranged parallel to the upper surface of said first ceramic substrate,

(b-3) a second ceramic substrate joined to an upper surface of said first region of said first metal plate, and

(b-4) a second metal plate joined to an upper surface of said second ceramic substrate and formed into a predetermined pattern,

said semiconductor device further comprising;

(c) a power semiconductor device mounted on an upper surface of said second region of said first metal plate, and

(d) a control semiconductor device mounted on an upper surface of said second metal plate for controlling said power semiconductor device,

at least said second region of said first metal plate including;

(b-3-1) a first metal layer joined to the upper surface of said first ceramic substrate,

(b-3-2) a second metal layer bonded onto said first metal layer, and

(b-3-3) a third metal layer bonded onto said second metal layer,

said second metal layer being lower in coefficient of thermal expansion than said first and third metal layers,

said first region of said first metal plate being an electrode layer to be held at a constant potential.

2. The semiconductor device of claim 1, wherein an operation reference electrode of said power semiconductor device is connected electrically to said first region.

3. The semiconductor device of claim 2, wherein said first region is an electrode layer to be grounded.

4. The semiconductor device of claim 3, wherein both of said first and second regions of said first metal plate have said first to third metal layers.

5. The semiconductor device of claim 2,

wherein said first and third metal layers are made of copper or copper alloy, and

wherein said second metal layer is made of molybdenum, tungsten, molybdenum alloy or tungsten alloy.

6. The semiconductor device of claim 5, further comprising:

(e) a case for covering said composite substrate, said power semiconductor device and said control semiconductor device and bonded to said metal base plate, and

(f) a sealing material filling the interior of said case for sealing said composite substrate, said power semiconductor device and said control semiconductor device.

7. The semiconductor device of claim 4,

wherein said second metal plate includes:

(b-4-1) a fourth metal layer,

(b-4-2) a fifth metal layer bonded onto said fourth metal layer, and

(b-4-3) a sixth metal layer bonded onto said fifth metal layer, and

wherein said fifth metal layer is lower in coefficient of thermal expansion than said fourth and sixth metal layers.

8. The semiconductor device of claim 7,

wherein said fourth and sixth metal layers are made of copper or copper alloy, and

wherein said fifth metal layer is made of molybdenum, tungsten, molybdenum alloy, or tungsten alloy.

9. The semiconductor device of claim 4,

wherein said composite substrate further includes

(b-5) a third metal plate fitted between said first ceramic substrate and said metal base plate,

wherein said third metal plate includes:

(b-5-I) a seventh metal layer,

(b-5-2) an eighth metal layer bonded onto said seventh metal layer, and

(b-5-3) a ninth metal layer bonded onto said eighth metal layer, and

wherein said eighth metal layer is lower in coefficient of thermal expansion than said seventh and ninth metal layers.

10. The semiconductor device of claim 9,

wherein said seventh and ninth metal layers are made of copper or copper alloy, and

wherein said eighth metal layer is made of molybdenum, tungsten, molybdenum alloy, or tungsten alloy.

11. The semiconductor device of claim 3, wherein said first region of said first metal plate is made of a substantially single metal.

12. The semiconductor device of claim 11, wherein said first region is made of copper or copper alloy.

13. A semiconductor device, comprising:

(a) a metal base plate,

(b) a composite substrate mounted on said metal base plate,

said composite substrate including;

(b-1) a first ceramic substrate joined onto said metal base plate,

(b-2) a first metal plate joined to an upper surface of said first ceramic substrate and formed into a predetermined pattern, said first metal plate having first and second regions arranged parallel to the upper surface of said first ceramic substrate,

(b-3) a second ceramic substrate joined to an upper surface of said first region of said first metal plate, and

(b-4) a second metal plate joined to an upper surface of said second ceramic substrate and formed into a predetermined pattern,

said semiconductor device further comprising;

(c) a power semiconductor device mounted on an upper surface of said second region of said first metal plate, and

(d) a control semiconductor device mounted on an upper surface of said second metal plate for controlling said power semiconductor device,

at least said second region of said first metal plate including;

(b-3-1) a first metal layer joined to the upper surface of said first ceramic substrate,

(b-3-2) a second metal layer bonded onto said first metal layer, and

(b-3-3) a third metal layer bonded onto said second metal layer,

said second metal layer being lower in coefficient of thermal expansion than said first and third metal layers.

14. A composite substrate for use in a semiconductor device comprising:

(a) a first ceramic substrate,

(b) a first metal plate joined to an upper surface of said first ceramic substrate and having first and second regions arranged parallel to the upper surface of said first ceramic substrate,

(c) a second ceramic substrate joined onto said first region of said first metal plate,

(d) a second metal plate joined to an upper surface of said second ceramic substrate, and

(e) a third metal plate joined to a lower surface of said first ceramic substrate,

at least said second region of said first metal plate including;

(b-1) a first metal layer,

(b-2) a second metal layer bonded onto said first metal layer, and

(b-3) a third metal layer bonded onto said second metal layer,

said second metal layer being lower in coefficient of thermal expansion than said first and third metal layers.

15. The composite substrate of claim 14, wherein both of said first and second regions of said first metal plate have said first to third metal layers.

16. The composite substrate of claim 15,

wherein said first and third metal layers are made of copper or copper alloy, and

wherein said second metal layer is made of molybdenum, tungsten, molybdenum alloy, or tungsten alloy.

17. The composite substrate of claim 14,

wherein said second metal plate includes:

(d-I) a fourth metal layer,

(d

     2) a fifth metal layer bonded onto said fourth metal layer, and

(d

     3) a sixth metal layer bonded onto said fifth metal layer, and

wherein said fifth metal layer is lower in coefficient of thermal expansion than said fourth and sixth metal layers.

18. The composite substrate of claim 17,

wherein said fourth and sixth metal layers are made of copper or copper alloy, and

wherein said fifth metal layer is made of molybdenum, tungsten, molybdenum alloy, or tungsten alloy.

19. The composite substrate of claim 17,

wherein said third metal plate includes:

(e-1) a seventh metal layer,

(e-2) an eighth metal layer bonded onto said seventh metal layer, and

(e-3) a ninth metal layer bonded onto said eighth metal layer, and

wherein said eighth metal layer is lower in coefficient of thermal expansion than said seventh and ninth metal layers.

20. The composite substrate of claim 19,

wherein said seventh and ninth metal layers are made of copper or copper alloy, and

wherein said eighth metal layer is made of molybdenum, tungsten, molybdenum alloy, or tungsten alloy.