Coherent side lobe canceler
First Claim
1. A coherent sidelobe canceler for communications systems providing effective continued operation within environments of large clutter and high pulse interference comprising:
- A plurality of CSLC loops, each having;
CSLC correlation filter means responsive inclusively to a CSLC residue output signal and a CSLC INHIBIT signal,CSLC limiter means responsive to an auxiliary input signal and providing a limited output signal to said correlation filter means,CSLC vector modulator means inclusively responsive to said auxiliary input signal and a signal provided as output from said CSLC correlation filter means;
CSLC summing means responsive to the signal outputs from said vector modulator means and furnishing an output signal;
CSLC subtractor means responsive to a main input signal and the output signal furnished by said CSLC summing means;
CSLC sensing circuit means responsive to said CSLC residue and generating said CSLC INHIBIT signals.
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Accused Products
Abstract
The elimination of jamming signals from received radar signals is conventionally accomplished by side lobe cancellation techniques. Large interfering signals caused either by clutter or other sources, however, can cause intolerable degradation of coherent side lobe cancellation (CSLC) systems. In the present invention an inhibit signal is used to open the input to the coherent side lobe cancellation error sensing circuits thus preventing large signals from entering the coherent side lobe cancellation loop. Large signals entering coherent side lobe cancellation loops give rise to erroneous transients in the output. The invention effects storage of previously sensed error signals so as to continue jammer cancellation until new data become available to update the error signals. The inhibit signal is generated by a combination of coherent side lobe cancellation sensing circuits and logic control circuits that determine when an inhibit signal should be generated. When an inhibit signal is not present, the coherent side lobe cancellation loop operates in its normal fashion. During intervals when excessive clutter or signal is present on the main channel, an inhibit signal is generated causing the occurrence of two actions in the coherent side lobe cancellation loop. First, the inhibit signal opens a switch at the output of the correlation mixer so that no input is accepted into the coherent side lobe cancellation loop for a time interval, thereby preventing the large signal from disturbing the loop operation. Second and simultaneously, the inhibit signal causes a sample-and-hold circuit to sample the loop filter output thereby preventing the loops from relaxing during this time interval.
19 Citations
16 Claims
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1. A coherent sidelobe canceler for communications systems providing effective continued operation within environments of large clutter and high pulse interference comprising:
A plurality of CSLC loops, each having; CSLC correlation filter means responsive inclusively to a CSLC residue output signal and a CSLC INHIBIT signal, CSLC limiter means responsive to an auxiliary input signal and providing a limited output signal to said correlation filter means, CSLC vector modulator means inclusively responsive to said auxiliary input signal and a signal provided as output from said CSLC correlation filter means; CSLC summing means responsive to the signal outputs from said vector modulator means and furnishing an output signal; CSLC subtractor means responsive to a main input signal and the output signal furnished by said CSLC summing means; CSLC sensing circuit means responsive to said CSLC residue and generating said CSLC INHIBIT signals. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A coherent sidelobe canceler for communications systems comprising:
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CSLC subtractor means responsive to a main input signal and coupled to a main receiver and to the input of first amplifier means, comparison means coupled to the output at said first amplifier means, first threshold selection means coupled to the output of said first amplifier means, second amplifier means responsive to auxiliary channel input signals and coupled to said comparison means, fast time constant circuit means responsive to an output signal from said second amplifier means, second threshold selection means coupled to said output signal from said second amplifier means, first logic gating means responsive to an output signal from said comparison means and said fast time constant circuit means, third threshold selection means responsive to a moving target indicator residue signal, counter means coupled to said third threshold selection means, bistable circuit means coupled to said counter means, logic control circuit means responsive inclusively to output signals from said first threshold selection means, said comparison means, said first logic gating means, said second threshold selection means and said bistable circuit means. - View Dependent Claims (11, 12, 13, 14, 15, 16)
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Specification