Vertical synchronization processing circuit
First Claim
1. A vertical synchronization processing circuit comprising:
- a counter for counting a clock signal synchronized with a horizontal sync signal;
means for resetting said counter in response to a vertical synchronization signal within a predetermined limit so as to prohibit reset due to a non-standard signal;
means for storing the data counted at the timing of reset; and
means for changing a predetermined limit prohibiting reset due to a non-standard signal according to the data from said storing means.
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Accused Products
Abstract
A vertical synchronization processing circuit includes a counter for counting a clock signal synchronized with a horizontal sync. signal, a circuit for resetting the counter in response to a vertical synchronization signal within a predetermined limit prohibiting reset due to a non-standard signal, a memory for storing the data counted at the timing of reset, and a circuit for changing a predetermined limit prohibiting reset due to a non-standard signal according to the data from the memory. A circuit for discriminating an existence of a vertical synchronization interval can also be provided along with a second resetting circuit for resetting the counter if the discriminating circuit detects the existence of the vertical synchronization interval when the counter counts a predetermined number of clock signals in case there is not a vertical synchronization pulse within the predetermined limit.
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Citations
4 Claims
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1. A vertical synchronization processing circuit comprising:
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a counter for counting a clock signal synchronized with a horizontal sync signal; means for resetting said counter in response to a vertical synchronization signal within a predetermined limit so as to prohibit reset due to a non-standard signal; means for storing the data counted at the timing of reset; and means for changing a predetermined limit prohibiting reset due to a non-standard signal according to the data from said storing means. - View Dependent Claims (2, 3)
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4. A vertical synchronization processing circuit comprising:
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a counter for counting a clock signal synchronized with a horizontal sync signal; first resetting means for resetting said counter in response to a vertical synchronization pulse within a predetermined limit prohibiting reset due to a non-standard signal; means for discriminating an existence of a vertical synchronization interval; second resetting means for resetting said counter if said discriminating means detects the existence of the vertical synchronization interval when said counter counts a predetermined number of clock signals in case that there is not a vertical synchronization pulse within said predetermined limit; means for storing the data counted at the timing of resetting the counter; and means for changing the predetermined limit prohibiting reset due to a non-standard signal according to the data from said storing means.
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Specification