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Vertical synchronization processing circuit

  • US 5,291,287 A
  • Filed: 05/27/1992
  • Issued: 03/01/1994
  • Est. Priority Date: 05/28/1991
  • Status: Expired due to Term
First Claim
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1. A vertical synchronization processing circuit comprising:

  • a counter for counting a clock signal synchronized with a horizontal sync signal;

    means for resetting said counter in response to a vertical synchronization signal within a predetermined limit so as to prohibit reset due to a non-standard signal;

    means for storing the data counted at the timing of reset; and

    means for changing a predetermined limit prohibiting reset due to a non-standard signal according to the data from said storing means.

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