Interprocessor switching network

• US 5,291,489 A
• Filed: 02/12/1992
• Issued: 03/01/1994
• Est. Priority Date: 11/13/1987
• Status: Expired due to Term

• Current Assignee: Alcatel-Lucent USA, Inc. (Nokia Corporation)
• Original Assignee: DSC Communications Corp. (Nokia Corporation)
• Inventors: Morgan, James D., Adams, Allen R. Jr., Nimon, Robert E., Read, Edgar L.
• Primary Examiner(s): Olms, Douglas W.
• Assistant Examiner(s): TON, DANG T
• Application Number:
  US07/836,175
• Time in Patent Office: 748 Days
• Field of Search: 370/85.1, 370/95.1, 370/95.2, 370/110.1, 370/85.8, 370/85.6, 370/60, 370/94.1, 370/94.3, 340/825.08, 340/825.5, 340/825.51, 364/431.12, 364/431.04, 395/725, 395/425, 395/500, 395/800, 395/325, 379/96, 379/269
• US Class Current: 370/401
• CPC Class Codes: G06F 11/08 Error detection or correction by redundancy in data representation, e.g. by using checking codes
• CPC Class Codes: G06F 11/10 Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
• CPC Class Codes: G06F 11/16 Error detection or correction of the data by redundancy in hardware
• CPC Class Codes: G06F 11/22 Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
• CPC Class Codes: H04L 12/5601 Transfer mode dependent, e.g. ATM
• CPC Class Codes: H04L 2012/5627 Fault tolerance and recovery
• CPC Class Codes: H04L 49/40 Constructional details, e.g. power supply, mechanical construction or backplane
• CPC Class Codes: H04L 49/552 by ensuring the integrity of packets received through redundant connections
• CPC Class Codes: H04L 49/555 Error detection
• CPC Class Codes: H04L 49/557 Error correction, e.g. fault recovery or fault tolerance
• CPC Class Codes: H04Q 11/0407 using a stored programme control

Abstract

A message transport network (10) is provided for high speed switching between processing elements (72, 80). Clusters of low speed processing elements (72) may be connected to the message transport network (10) through a transport node controller (78). The transport node controller (78) and the high speed processors (80) are connected to the gateways (82). A pair of gateways (82) may be connected through a transport interchange node (106) to allow communication between processors (72, 80) associated with the gateways (82). A transport interchange supervisor (98) maintains a record of the status of each gateway (82) and generates commands to form connection between gateways (82) in the transport interchange node (106). A maintenance controller (102) and system maintenance processor (76) oversee the validity of the data being passed through the system on paths independent of the data transfer paths. The message transport network (10) may be used in variety of applications, such as a telephony switch (11), a signaling transfer point system (21) or a fault tolerant minicomputer (49).

Claims

1. Communication circuitry for a plurality of processors, comprising:

first transfer circuitry responsive to program code and capable of transferring interprocessor communications between a predetermined first set of said plurality of processors,

second transfer circuitry responsive to program code and capable of transferring interprocessor communications between said predetermined first set of said plurality of processors and at least a second set of said plurality of processors and operable to allow simultaneous and distinct communications among said plurality of processors, and

control circuit for sensing changes in at least one of said plurality of processors and for responding to said sensed changes by dynamically modifying said program code for at least one of said first and second transfer circuitry.

2. The circuitry of claim 1, wherein said first transfer circuitry includes an associated first instruction memory for containing said program code.

3. The circuitry of claim 2, wherein said first instruction memory is connected to said control circuitry.

4. The circuitry of claim 3, wherein said first instruction memory is divided into a plurality of sections corresponding to processors in said first set of said plurality of processors.

5. The circuitry of claim 4, wherein said control circuitry is operable to modify a section of said plurality of sections of said first instruction memory associated with one of said processors to initiate a communication therefrom.

6. The circuitry of claim 4, wherein said control circuitry is operable to modify a section of said plurality of sections of said first instruction memory associated with one of said processors to enable a communication therewith.

7. The circuitry of claim 1, wherein said second transfer circuitry includes an associated second instruction memory for containing said program code.

8. The circuitry of claim 7, wherein said second instruction memory is connected to said control circuitry.

9. The circuitry of claim 7, wherein said second instruction memory has predefined sections associated with predetermined ones of said processors.

10. The circuitry of claim 9, wherein said control circuitry is operable to modify one or more of said predefined sections of said second instruction memory to indicate that the respective associated processors are not ready to receive a communication.

11. The circuitry of claim 1, further comprising:

a memory interconnected with said first transfer circuitry and said second transfer circuitry for temporarily storing communications between said plurality of processors.

12. The circuitry of claim 11, further comprising:

circuitry interconnected with said control circuitry for monitoring the performance and operating status of said first and second transfer circuitry, said control circuitry, and said memory.

13. The circuitry of claim 11, wherein said control circuitry is operable to provide said first transfer circuitry a starting address in said memory at which a communication from a first one of said processors in said predetermined first set of said plurality of processors may be stored.

14. The circuitry of claim 13, wherein said control circuitry is further operable to provide said first transfer circuitry with a number indicating the number of bytes of data in said communication from said first one of said processors.

15. The circuitry of claim 14, wherein said control circuitry is operable to provide a starting address and byte count information to said second transfer circuitry for a communication in said memory to be transferred to one of said processors in said at least second set of said plurality of processors.

16. The circuitry of claim 11, wherein said predetermined first set of said plurality of processors and said first transfer circuitry are interconnected by a bus.

17. The circuitry of claim 16, wherein said first transfer circuitry includes direct memory access circuitry interconnected between said bus and said memory.

18. The circuitry of claim 16, wherein said first transfer circuitry includes circuitry for detecting status information generated by a first processor in said predetermined first set of said plurality of processors to initiate a communication to a second processor in said at least second set of said plurality of processors.

19. The circuitry of claim 11, wherein said second transfer circuitry includes direct memory access circuitry connected to said memory.

20. The circuitry of claim 1, further comprising:

a first signal line connected to said control circuitry for use during communications between said predetermined first set of said plurality of processors and said at least second set of said plurality of processors.

21. The circuitry of claim 1, wherein said predetermined first set of said plurality of processors and said first transfer circuitry are interconnected by a bus.

22. The circuitry of claim 1, wherein said first transfer circuitry includes circuitry for detecting status information generated by at least a first one of said processors in said predetermined first set of said plurality of processors to initiate a communication to a second processor in said plurality of processors.

23. The circuitry of claim 22, further comprising:

circuitry for transferring said status information from said first transfer circuitry to said control circuitry.

24. The circuitry of claim 23, wherein said circuitry for transferring said status information includes a fifo memory.

25. The circuitry of claim 1, wherein said second transfer circuitry includes circuitry to specify one of said processors in said at least second set of said plurality of processors with which a communication may be made.

26. The circuitry of claim 25, wherein said second transfer circuitry includes circuitry to detect a signal indicating that a specified processor is operable to receive a communication.

27. The circuitry of claim 1, wherein said second transfer circuitry is operable to receive a request to initiate a communication with one of said processors of said first set of said plurality of processors from a processor in said at least second set of said plurality of processors.

28. The circuitry of claim 27, wherein said second transfer circuitry is operable to initiate a communication in response to said request to initiate.

29. The circuitry of claim 1, wherein said second transfer circuitry is operable to generate a request to initiate a communication from one of said processors of said first set of said plurality of processors with a processor in said at least second set of said plurality of processors.

30. The circuitry of claim 1, wherein said first transfer circuitry includes circuitry for polling at least one of said processors in said predetermined first set of said plurality of processors to detect status information generated by a first one of said at least one of said processors in said predetermined first set of processors to initiate a communication with a second processor.

31. The circuitry of claim 1, wherein said second transfer circuitry includes circuitry for enabling a communication responsive to said first transfer circuitry polling at least one of said processors in said predetermined first set of said plurality processor to detect a signal indicating that at least one of said processors is operable to receive a communication.

32. The circuitry of claim 1, wherein said second transfer circuitry includes at least one signal line for use during communications between one or more of said processors in said predetermined first set of said plurality of processors and one or more processors in said at least second set of said plurality of processors.

33. The circuitry of claim 1, wherein said control circuitry includes a microprocessor.

34. The circuitry of claim 1, wherein said second transfer circuitry includes circuitry responsive to at least one processor in said at least second set of said plurality of processors to initiate a communication with at least one processor in said predetermined first set of said plurality of processors.

35. The circuitry of claim 1, wherein said second transfer circuitry includes circuitry responsive to at least one processor in said at least second set of said plurality of processors to receive a communication from at least one processor in said predetermined first set of said plurality of processors.