Methods and apparatus for hard disk emulation

• US 5,291,584 A
• Filed: 07/23/1991
• Issued: 03/01/1994
• Est. Priority Date: 07/23/1991
• Status: Expired due to Term

• Current Assignee: Winbond Electronics Corporation
• Original Assignee: Nexcom Technology, Inc. (Uphill Investment Co.)
• Inventors: Challa, Nagesh, Gannage, Michel E.
• Primary Examiner(s): Harrell, Robert B.
• Application Number:
  US07/734,414
• Time in Patent Office: 952 Days
• Field of Search: 364/DIG. 1 MS File, 364/DIG. 2 MS File, 364/, 395/500, 395/800, 365/189.01, 365/189.12, 365/221, 365/222, 365/230.01, 365/244
• US Class Current: 703/24
• CPC Class Codes: G06F 3/0601 Interfaces specially adapted for storage systems
• CPC Class Codes: G06F 3/0664 at device level, e.g. emulation of a storage device or system
• CPC Class Codes: G11C 7/1075 for multiport memories each having random access ports and serial ports, e.g. video RAM

Abstract

A magnetic media hard disk is emulated in a solid state hard disk having a disk controller, a data buffer, a microcontroller, and a disk emulator section. The disk emulator section includes a disk emulator interface and a memory array. The architecture of the memory array includes a number of memory banks which typically correspond to respective sectors of the emulated hard disk, but could correspond to respective groups of sectors of the emulated hard disk. Each of the memory banks has its own serial data line and its own serial clock line, and include a number of serial memory devices that connect to the bank serial data line and bank clock line with respective serial data and clock lines. Each of the serial memory devices also has a static address corresponding to a head address of the emulated hard disk. At any given time, one of the memory banks is selected by activation of its clock line based on the sector addressed, and one of the serial memory devices in the bank responds based on a comparison of its static address with head address data communicated on the serial data line. Other features described include serial memory device start sequences and bad bit replacement.

Claims

1. A solid state apparatus for emulating a hard disk having a plurality of tracks per head and a plurality of sectors per track, comprising:

a plurality of groups of solid state memory cells arranged in a plurality of banks,

each emulated sector and head being represented by a memory cell group having a predetermined sector association, a predetermined head association, and a static address corresponding to said head association;

said memory cell groups having respective group serial buses and respective group clock buses, and

memory cell groups with a common sector association being members of a common bank, said respective group serial buses being interconnected to form a common bank serial bus, and said respective group clock buses being interconnected to form a common bank clock bus; and

an interface for communicating disk control signals and data with a hard disk control system, and for communicating serial and clock signals to said memory cells over, respectively, an emulator serial bus connected to said bank serial buses, and an emulator clock bus connected to said bank clock buses;

wherein at least one of said emulator serial bus and said emulator clock bus comprises a number of lines equal to the plurality of banks for communicating with a selected memory cell group that is within a bank corresponding to a hard disk sector.

2. An apparatus as in claim 1, wherein each of said memory cell groups has a static address corresponding to a hard disk head, and wherein head selection data is communicated over said emulator serial bus for rendering a selected memory cell group responsive to clock signals for clocking serial information upon a march of the static address thereof with said head selection data.

3. An apparatus as in claim 2, wherein:

said emulator serial bus comprises a number of lines equal to the number of sectors, the lines of said emulator serial bus being respectively connected to said bank serial buses; and

said emulator clock bus comprises a number of lines equal to the number of sectors, the lines of said emulator clock bus being respectively connected to said bank clock buses.

4. An apparatus as in claim 2, wherein:

each of said memory cell groups comprises a plurality of serial memory devices;

each of said serial memory devices comprises a device serial bus;

a device clock bus;

a static head address; and

a static track range address; and

head selection data and track range data are communicated over said emulator serial bus for rendering a selected serial memory device within a selected memory cell group responsive to clock signals for clocking serial information upon a match of the static address thereof with said head selection data, and the static track range address thereof with said track range data.

5. An apparatus as in claim 1 wherein said banks correspond to respective sectors of said emulated hard disk.

6. An apparatus as in claim 1 wherein said banks correspond to respective plurality of sectors of said emulated hard disk.

7. A solid state apparatus for emulating a hard disk having a plurality of tracks per head and a plurality of sectors per track, comprising:

a plurality of serial memory devices, each having a serial bus and a clock bus; and

an interface for communicating disk control signals and data with a hard disk control system, and for selecting among the respective pairs of serial buses and clock buses of said serial memory devices in accordance with hard disk sector information for communicating serial information and clock signals to a group of said serial memory devices.

8. An apparatus as in claim 7, wherein:

each of said serial memory devices comprises a predetermined number of words;

each of said groups of serial memory devices comprises "N" unique ones of said serial memory devices, N corresponding to the number of tracks being emulated divided by the number of words per serial memory device, the serial memory devices of each of said groups having their respective serial data ports connected to a group data bus, and having their respective clock ports connected to a group clock bus; and

said interface selects from among the respective pairs of group serial data buses and group clock buses.

9. An apparatus as in claim 8, wherein:

the value of N is greater than one;

the serial memory devices within each of said groups include respective unique static addresses, and;

each of said serial memory devices comprise comparator logic for permitting memory access thereto if an address received over the serial data bus thereof matches the static address thereof, and for preventing memory access thereto if an address received over the serial data bus thereof fails to match the static address thereof.

10. An apparatus as in claim 9, wherein said static addresses correspond to ranges of tracks.

11. An apparatus as in claim 9, wherein said static addresses correspond to head numbers.

12. An apparatus as in claim 9, wherein said static addresses correspond to head numbers and ranges of tracks within a head.

13. An apparatus as in claim 7, wherein each of said serial memory devices includes an address acquisition means.

14. An apparatus as in claim 13, wherein:

each of said groups of serial memory devices comprises a plurality of unique ones of said serial memory devices;

each of said serial memory devices comprises counter logic having a carry input and a carry output, said each serial memory device being operative during first and second states of said carry input and carry output to count clock pulses, and being operative upon the occurrence of a third state of said carry input and carry output to latch the number of clock pulses counted as a bank address;

the serial memory devices within each of said groups have their respective serial data ports connected to a group data bus, their respective clock ports connected to a group clock bus, and their respective carry inputs and carry outputs connected serially such that the carry input of a first one of the serial memory devices is connected to a predetermined logic level, and the carry inputs of the other serial memory devices are connected to the carry outputs of the respective preceding serial memory devices; and

the counter logic of each of said serial memory devices is responsive to said second state to cause a transition to said third state upon one clock pulse during an address acquisition mode.

15. An apparatus as in claim 7, wherein each of said serial memory devices further comprises:

means for detecting a continuous low state for a predetermined interval both on the associated serial data line and on the associated clock line; and

means responsive to said detecting means for indicating a start condition upon a low to high transition on said associated clock line.

16. An apparatus as in claim 15, wherein said continuous low state both on the associated serial data line and on said associated clock line represent an idle state commanded by said interface.

17. An apparatus as in claim 7, wherein each of said groups of serial memory devices comprises a unique one of said serial memory devices.

18. An apparatus as in claim 7, wherein:

each of said serial memory devices comprises a plurality of words of a predetermined length and counter logic having a carry input and a carry output, said each serial memory device being in a deny memory access state during first and third states of said carry input and carry output, and being in an allow memory access state during a second state of said carry input and carry output;

each of said groups of serial memory devices comprises "N" unique ones of said serial memory devices, N being an integer corresponding to the sector size in bits divided by said predetermined word length in bits;

the serial memory devices within each of said groups have their respective serial data ports connected to a group data bus, their respective clock ports connected to a group clock bus, and their respective carry inputs and carry outputs connected serially such that the carry input of a first one of the serial memory devices is connected to a predetermined logic level, and the carry inputs of the other serial memory devices are connected to the carry outputs of the respective preceding serial memory devices;

the counter logic of each of said serial memory devices is responsive to said second state to cause a transition to said third state upon a number of clock pulses equal to said word length; and

said interface selects from among the respective pairs of group serial data buses and group clock buses.

19. An apparatus as in claim 7, wherein each of said serial memory devices further comprises:

a timer for determining an interval;

means for detecting a high to low signal transition on the associated serial data line while the signal level on the associated clock line is low;

means responsive to said detecting means for initiating said timer; and

means responsive to said timer for confirming a start condition if no transition occurs on said clock line during said interval, and for invalidating said start condition if a transition occurs on said clock line during said interval.

20. A method for emulating a hard disk having a plurality of tracks per head and a plurality of sectors per track, comprising:

arranging a plurality of solid state memory arrays into banks having respective sector associations, the banks having respective associated serial-clock bus pairs;

assigning the solid state memory arrays respective head associations;

activating a selected one of the serial-clock bus pairs to access the solid state memory arrays in a particular one of the banks; and

transmitting a head identifier on the selected serial bus to access a particular one of the solid state memory arrays in the particular bank.

21. A method as in claim 20 further comprising the step of transmitting a track address on the selected serial bus to access a particular data field in the particular solid state memory array.

22. A method as in claim 21 further comprising, prior to the head identifier transmitting step and the track address transmitting step, the step of transmitting a start sequence on the selected serial bus.

23. A method as in claim 20 further comprising the steps of:

transmitting a start sequence on the selected serial bus;

driving a clock signal onto the selected clock bus;

clocking an opcode into the particular solid state memory on the selected serial bus in accordance with the clock signal;

clocking a row address into the particular solid state memory on the selected serial bus in accordance with the clock signal; and

clocking a data field into a particular address of the particular solid state memory on the selected serial bus in accordance with the row address and the clock signal.

24. A method as in claim 20 further comprising the steps of:

transmitting a start sequence on the selected serial bus;

driving a clock signal onto the selected clock bus;

clocking an opcode into the particular solid state memory on the selected serial bus in accordance with the clock signal;

clocking a row address into the particular solid state memory on the selected serial bus in accordance with the clock signal; and

clocking a data field from a particular address of the particular solid state memory on the selected serial bus in accordance with the row address and the clock signal.

25. An apparatus for emulating a hard disk having a plurality of tracks per head and a plurality of sectors per track, comprising:

means for arranging a plurality of solid state memory arrays into banks having respective sector associations, the banks having respective associated serial-clock bus pairs;

means for assigning the solid state memory arrays respective head associations;

means for activating a selected one of the serial-clock bus pairs to access the solid state memory arrays in a particular one of the banks; and

means for transmitting a head identifier on the selected serial bus to access a particular one of the solid state memory arrays in the particular bank.