Computer interface circuit

• US 5,291,609 A
• Filed: 12/23/1992
• Issued: 03/01/1994
• Est. Priority Date: 06/13/1991
• Status: Expired due to Term

• Current Assignee: Sony Electronics Inc. (Sony Group Corp.)
• Original Assignee: Sony Electronics Inc. (Sony Group Corp.)
• Inventors: Herz, William S.
• Primary Examiner(s): Fleming, Michael R.
• Assistant Examiner(s): Hafiz, Tariq R.
• Application Number:
  US07/996,836
• Time in Patent Office: 433 Days
• Field of Search: 395/575, 395/200, 395/325, 395/500, 395/575, 395/725
• US Class Current: 710/52
• CPC Class Codes: G06F 13/24 using interrupt G06F13/32 takes precedence
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices

Abstract

An interface circuit for providing asynchronous interrupt service for multiple peripheral devices in accordance with instructions from a host computer includes two dual universal asynchronous receivers-transmitters ("UARTs"), a dual port random-access memory ("RAM") and a microprocessor ("μP"). The dual UARTs selectively read data separately from selected peripheral devices and selectively write that data to the dual port RAM for access by the host computer, and read data from the dual port RAM as stored therein by the host computer and write that data to a selected peripheral device, in accordance with addresses from the μP. Following initiation of an interrupt sequence, the dual port RAM allows the host computer to selectively and asynchronously read data (e.g. from a peripheral device via a dual UART) therefrom and write necessary data or instructions (e.g. for the μP or a peripheral device via a dual UART) thereto for the μP to asynchronously provide interrupt service to the peripheral devices. This interface circuit configuration minimizes idle time for the host computer during interrupt servicing by the μP.

Claims

1. An interface circuit for providing asynchronous communication and control between a host computer and at least one peripheral device, the interface circuit comprising:

transceiver means for receiving a first internal memory address and in accordance therewith receiving peripheral device input data from and transmitting peripheral device output data to at least one peripheral device;

memory means coupled to the transceiver means for receiving a second internal memory address and in accordance therewith reading the peripheral device input data from and writing the peripheral device output data to the transceiver means and further for receiving an external memory address via an external address port and in accordance therewith reading host computer input data from and writing host computer output data to a host computer; and

computer means coupled to the transceiver means and the memory means for providing the first and second internal memory addresses thereto, respectively;

wherein the first internal memory address, the second internal memory address and the external memory address are each distinct from one another.

2. An interface circuit as recited in claim 1, further comprising a data bus coupling the transceiver means and the memory means.

3. An interface circuit as recited in claim 1, further comprising an address bus coupling the computer means, the transceiver means and the memory means.

4. An interface circuit as recited in claim 1, wherein the memory means selectively reads the host computer input data and writes the host computer output data asynchronously with respect to the reading of the received peripheral device input data and the writing of the peripheral device output data.

5. An interface circuit as recited in claim 1, wherein the transceiver means comprises a universal asynchronous receiver-transmitter.

6. An interface circuit as recited in claim 1, wherein the memory means comprises a dual port random access memory.

7. An interface circuit as recited in claim 1, wherein the computer means comprises a microprocessor.

8. An interface circuit for providing asynchronous interrupt service for a plurality of peripheral devices in accordance with control data from a host computer, the interface circuit comprising:

a data bus;

an address bus;

a data transceiver which includes a first address port coupled to the address bus for receiving a plurality of transceiver addresses therefrom, and which includes a plurality of external data ports for selectively receiving peripheral device input data from and providing peripheral device output data to a plurality of peripheral devices in accordance with the received plurality of transceiver addresses, and which further includes a first data port coupled to the data bus for providing the received peripheral device input data thereto and receiving the peripheral device output data therefrom in accordance with the received plurality of transceiver addresses;

a memory which includes a second address port coupled to the address bus for receiving a plurality of internal memory address therefrom, and which includes a third address port for receiving a plurality of external memory addresses, and which further includes a second data port for reading host computer input data from and writing host computer output data to a host computer in accordance with the received plurality of external memory addresses, and which still further includes a third data port coupled to the data bus for writing the host computer input data thereto and reading the host computer output data therefrom in accordance with the received plurality of internal memory addresses; and

a computer which includes a fourth address port coupled to the address bus for selectively providing the pluralities of transceiver and internal memory addresses thereto, and which further includes a fourth data port coupled to the data bus for selectively receiving the received peripheral device input data and the written host computer input data therefrom;

wherein the plurality of transceiver addresses, the plurality of internal memory addresses and the plurality of external memory addresses are each distinct from one another.

9. An interface circuit as recited in claim 8, wherein the memory selectively reads the host computer input data and writes the host computer output data asynchronously with respect to the reading of the host computer output data and the writing of the host computer input data.

10. An interface circuit as recited in claim 8, wherein the data transceiver comprises a plurality of universal asynchronous receivers-transmitters.

11. An interface circuit as recited in claim 8, wherein the memory comprises a dual port random access memory.

12. An interface circuit as recited in claim 8, wherein the computer comprises a microprocessor.