Real-time, concurrent, multifunction digital signal processor subsystem for personal computers

• US 5,291,614 A
• Filed: 09/03/1991
• Issued: 03/01/1994
• Est. Priority Date: 09/03/1991
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Dombrowski, Chris, Jensen, Eric, DeBauche, Bradley J., McCain, Melvin, Baker, Robert G., Massman, Lloyd H., Swingle, Paul R.
• Primary Examiner(s): Eng, David Y.
• Application Number:
  US07/753,505
• Time in Patent Office: 910 Days
• Field of Search: 395/275, 395/250, 395/325, 395/650, 395/800
• US Class Current: 712/35
• CPC Class Codes: G06F 9/4887 involving deadlines, e.g. rate based, periodic

Abstract

A personal computer system includes a digital signal processor (DSP) subsystem that is connectable to a plurality of application specific hardware devices. A single DSP is operable under a DSP real-time operating system (RTOS) to concurrently handle a plurality of different signal processing functions on a real-time basis. A DSP data store is connected to the DSP and to the personal computer and includes addressable locations that emulate addressable I/O registers associated with the application specific hardware devices to enable the personal computer to run a plurality of application programs controlling operation of the hardware devices. Performance is enhanced for I/O read and write operations by delaying halting of the DSP allowing such operations to complete in a cycle during which the DSP is not accessing the data store.

Claims

1. A personal computer comprising:

a main memory for storing application programs;

a first processor for executing said application programs;

a plurality of application specific hardware (ASH) devices;

a general purpose digital signal processing subsystem (DSPSS) connected to said ASH devices; and

bus means interconnecting said first processor, said main memory, and said DSPSS;

said DSPSS comprising

a plurality of ports connected to said ASH devices for transmitting analog signals and digital signals between said ASH devices and said DSPSS,

converter means for converting said analog signals into digital operands,

an instruction store connected to said DSP for storing a plurality of signal processing tasks for execution by said DSP,

a data store connected to said DSP and to said bus means so that said DSP and said first processor can independently access said data store, said data store being further connected to said ports and to said converter means for storing said digital operands and said digital signals,

a digital signal processor (DSP) for processing said digital signals and said digital operands, said DSP comprising an arithmetic logic unit and a multiplication unit for executing tasks to process said digital operands and said digital signals, and

control means connected to said DSP for operating said DSP and concurrently executing a plurality of said signal processing tasks in response to execution of said application programs by said first processor;

said control means comprising

a scheduling clock for generating a plurality of scheduling interrupts at fixed time intervals;

a plurality of task control blocks (TCBs) stored in said data store, there being a different TCB associated with each task, each TCB containing a plurality of fields for storing, for the associated task,

     1) a frame defining a scheduling period between successive scheduling of said associated task,

     2) a scheduling count defining when the associated task is to be next scheduled,

     3) DSP information for restoring said DSP when an interrupted task is next executed, and

     4) an instruction address at which to begin initial execution of said associated task;

a background executor for maintaining a queue of tasks scheduled for execution;

a foreground executor that is periodically executed in response to said scheduling interrupts for scheduling said tasks, said foreground director including means for

     1) saving DSP information from a task being interrupted,

     2) searching said unordered list of TCBs to find a TCB whose count field has reached a predetermined value,

     3) adding the task associated with such TCB, to said queue of tasks,

     4) updating said count field, in said TCB of the task added to said queue, by adding said frame to said count,

     5) ordering said tasks in said queue according to which tasks have the lowest counts in said TCBs associated therewith, with the task having the lowest count being at a head of said queue, and

     6) passing control to said background executor;

said background executor including means, operative in response to receiving control from said foreground executor, for passing control to said task at said head of said queue for execution thereof, for removing said task from said queue upon completion of execution thereof, and for passing control to the next task in line in said queue when another task has completed execution.

2. A personal computer in accordance with claim 1 wherein

said foreground director comprises means for first saving DSP information from a task being interrupted in response to read/write commands and to transmit/receive commands, and for then passing control to handlers for such commands.

3. A personal computer in accordance with claim 1

wherein each TCB further comprises a pointer field containing an address at which to resume execution of an interrupted associated task, and an interrupt field for indicating that the associated task has been interrupted;

and

said background executor includes means for transmitting said DSP information to said DSP from the TCB associated with the task at the head of the queue, and for passing control to the task at the head of said queue by branching to said address in said pointer field of said associated TCB, when said interrupt field of such TCB indicates that the associated task has been interrupted.

4. A personal computer in accordance with claim 1 wherein said DSPSS further comprises:

a cycle counter;

analyzing means for determining whether or not said DSP is going to access said data store in an immediately succeeding cycle;

incrementing means for incrementing said counter when said analyzing means makes a positive determination;

means, operative in response to said counter reaching a predetermined count, for halting operation of said DSP after delaying for a number of cycles defined by said predetermined count, to thereby allow said data store to be accessed by;

and means for granting access to said data store in response to I/O commands from said first processor, when said analyzing means make a negative determination and when said DSP is halted.

5. A personal computer in accordance with claim 1 wherein:

said DSP includes interrupt control means for receiving a plurality of interrupts having different priority levels ranging from a lowest level to a highest level; and

said scheduling interrupts, generated by said scheduling clock, have the highest level of priority.

6. A personal computer in accordance with claim 1 wherein said foreground executor is itself a task having its own TCB in which said count thereof is set to zero, and said means in said foreground executor adds another task to said queue when said count in said TCB of said another task equals said count in said own TCB.