Process for lay-out of a semiconductor integrated circuit

• US 5,292,687 A
• Filed: 02/07/1992
• Issued: 03/08/1994
• Est. Priority Date: 02/08/1991
• Status: Expired due to Fees

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Isozaki, Tomoaki
• Primary Examiner(s): Thomas, Tom
• Assistant Examiner(s): Picardat, Kevin M.
• Application Number:
  US07/832,331
• Time in Patent Office: 760 Days
• Field of Search: 437/209, 437/206, 437/207, 437/219, 437/217, 364/491
• US Class Current: 716/122
• CPC Class Codes: H01L 2224/023 Redistribution layers [RDL] for bonding areas
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/06 of a plurality of bonding areas
• CPC Class Codes: H01L 2924/0001 Technical content checked by a classifier
• CPC Class Codes: H01L 2924/01015 Phosphorus [P]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01082 Lead [Pb]
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/1433 Application-specific integrated circuit [ASIC]

Abstract

A pad is provided outside a pad block. The most appropriate position is determined for the pad which is connected to the pad block. The pad block is arranged to be most appropriate in position relative to the pad, and a coordinate of the pad block is determined to be used for interconnection of internal regions of the pad block.

Claims

1. A process for lay-out of a semiconductor integrated circuit, comprising the steps of:

determining a coordinate of a pad position which is most appropriate in accordance with a lead frame for packaging said semiconductor integrated circuit and a chip size of said semiconductor integrated circuit;

arranging a pad at said coordinate;

connecting said pad to a pad block, said pad block being positioned to be most appropriate relative to said pad;

determining a coordinate of said pad block; and

connecting internal regions of said pad block in accordance with said coordinate of said pad block.

2. A process for lay-out of a semiconductor integrated circuit, according to claim 1, wherein:

said connecting of said pad to said pad block is carried out by a first automatic lay-out tool; and

said connecting of said internal regions is carried out by a second automatic lay-out tool.

3. A process for lay-out of a semiconductor integrated circuit, according to claim 1, wherein:

said connecting of said pad to said pad block is carried out between each of plural pads and a pad block.

4. A process for lay-out of a semiconductor integrated circuit, according to claim 1, wherein:

said pad is arranged at a position outside of said pad block.

5. A process for lay-out of a semiconductor integrated circuit, according to claim 1, wherein:

a plurality of pad blocks are arranged along vertical and horizontal sides of said semiconductor integrated circuit.

6. A process for lay-out of a semiconductor integrated circuit, according to claim 1, wherein:

at least one pad is arranged in a region corresponding to a corner block.