FET nonvolatile memory with composite gate insulating layer

• US 5,293,062 A
• Filed: 12/02/1991
• Issued: 03/08/1994
• Est. Priority Date: 05/25/1991
• Status: Expired due to Term

• Current Assignee: ROHM Co., Ltd.
• Original Assignee: ROHM Co., Ltd.
• Inventors: Nakao, Hironobu
• Primary Examiner(s): James, Andrew J.
• Assistant Examiner(s): Tang, Alice W.
• Application Number:
  US07/801,537
• Time in Patent Office: 827 Days
• Field of Search: 257/218, 257/249, 257/250, 257/263, 257/269, 257/270, 257/288, 257/506, 257/546, 257/635, 257/636, 257/637, 257/638, 257/640, 257/645, 257/324, 257/325, 257/326, 257/639 , 257/646, 257/649
• US Class Current: 257/638
• CPC Class Codes: H01L 29/512 the variation being parallel to the channel plane
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors

Abstract

A gate insulating layer, which is formed on a channel region of a semiconductor substrate and interposed between the semiconductor substrate and a gate electrode, consists of a first part and a second part adjoining each other. The first part includes an oxide lower layer and a nitride upper layer, and a second part includes a nitride lower layer and an oxide upper layer.

Claims

1. A field effect transistor nonvolatile memory having a gate insulating layer formed on a channel region of a semiconductor substrate and interposed between a gate electrode and the semiconductor substrate, said gate insulating layer comprising:

a first part including a first oxide layer formed on and in direct contact with the channel region and a first nitride layer formed between the gate electrode and the first oxide layer; and

a second part including a second nitride layer formed on and in direct contact with the channel region and a second oxide layer formed between the gate electrode and the second nitride layer;

wherein the first and second parts are arranged adjacent to each other between a source region and a drain region.

2. The nonvolatile memory of claim 1, wherein a plurality of first parts and a plurality of second parts are alternately arranged adjacent each other in the first direction.

3. The nonvolatile memory of claim 1, wherein the first and second oxide layers have a thickness not less than 30 Å

.

4. The nonvolatile memory of claim 1, wherein the first and second nitride layers have a thickness not more than 190 Å

.