Two-stage rail-to-rail operational amplifier

• US 5,293,136 A
• Filed: 09/17/1992
• Issued: 03/08/1994
• Est. Priority Date: 09/17/1992
• Status: Expired due to Term

• Current Assignee: SGS Thomson Microelectronics Inc (STMicroelectronics NV)
• Original Assignee: SGS Thomson Microelectronics Inc (STMicroelectronics NV)
• Inventors: Ryat, Marc H.
• Primary Examiner(s): Mullins, James B.
• Application Number:
  US07/946,764
• Time in Patent Office: 537 Days
• Field of Search: 330/252, 330/253, 330/255, 330/257, 330/258
• US Class Current: 330/258
• CPC Class Codes: H03F 2203/45508 the CSC comprising a voltage generating circuit as bias circuit for the CSC
• CPC Class Codes: H03F 3/3008 Bifet SEPP output stages
• CPC Class Codes: H03F 3/3032 using two SEPP driving stages
• CPC Class Codes: H03F 3/45121 Folded cascode stages
• CPC Class Codes: H03F 3/45179 using MOSFET transistors as the active amplifying circuit H03F3/45278 takes precedence
• CPC Class Codes: H03F 3/45219 Folded cascode stages
• CPC Class Codes: H03F 3/45278 using BiFET transistors as the active amplifying circuit

Abstract

A two-stage class-AB operational amplifier, that can be implemented either with bipolar or MOS transistors, includes a differential input circuit adapted to receive a differential input signal to produce an amplified differential output signal for application to first and second nodes. The differential input stage has a common-mode control circuit that produces first and second common-mode control voltages on the first and second nodes. The common-mode control voltages are combined with the amplified differential output signal on the first and second nodes to produce a first stage differential output signal. A high-swing output stage is connected to receive the first stage differential output signal. First and second current mirrors each have a mirror transistor to mirror an output current produced in response to the differential input signals on respective lines including the first and second nodes. The common-mode control circuit is in series with mirror transistors of the first and second current mirrors. A circuit clamps the first and second nodes at a voltage of 2V_BE below the supply voltage, and clamps the voltage at the second node at a voltage of 2V_BE above the reference potential, enabling the circuit to operate with improved power-supply rejection ratios.

Claims

1. An operational amplifier, comprising:

a differential input circuit adapted to receive a differential input signal to produce an amplified differential output signal for application to first and second nodes;

said differential input circuit having a common-mode control circuit that produces first and second common-mode control voltages on said first and second nodes, whereby said common-mode control voltages are combined with said amplified differential output signal on said first and second nodes to produce a first stage differential output signal;

and a high-swing output stage connected to receive the first stage differential output signal.

2. The operational amplifier of claim 1 further comprising first and second current mirrors each having a mirror transistor to mirror an output current produced in response to said differential input signals on respective lines including said first and second nodes, and wherein said common-mode control circuit is in series with mirror transistors of said first and second current mirrors.

3. The operational amplifier of claim 2 wherein the common-mode control voltages are multiplied with said differential input signal on said first and second nodes.

4. The operational amplifier of claim 2 wherein said high-swing output stage comprises a buffer stage connected to receive said first stage differential output signal and a pair of output transistors connected to produce an operational amplifier output.

5. The operational amplifier of claim 4 further comprising a class-AB mode being circuit for biasing said pair of output transistors.

6. The operational amplifier of claim 4 wherein said differential input circuit comprises a first pair of transistors of opposite conductivity type having control elements connected to receive one side of the differential input signal, and a second pair of transistors of opposite conductivity type having control elements connected to receive another side of the differential input signal.

7. The operational amplifier of claim 6 wherein said differential input circuit further comprises first and second current sources connected respectively between transistors of said first and second transistor pairs of a first conductivity type and a voltage supply, and between transistors of said first and second transistor pairs of a second conductivity type and a reference potential.

8. The operational amplifier of claim 4 wherein said operational amplifier is implemented with bipolar transistors.

9. The operational amplifier of claim 4 wherein said operational amplifier is implemented with MOS transistors.

10. An operational amplifier, comprising:

a differential input circuit adapted to receive a differential input signal to produce an amplified differential output signal on first and second nodes;

said differential input circuit having a common-mode control circuit that produces first and second common-mode control voltages on said first and second nodes, whereby said common-mode control voltages are combined with said amplified differential output signal on said first and second nodes to produce a first stage differential output signal;

a circuit for clamping the first and second nodes at a predetermined level with respect to the supply voltage and reference potential;

and a high-swing output stage connected to receive the first stage differential output signal.

11. The operational amplifier of claim 10 wherein the common-mode control voltages are multiplied with said differential input signal on said first and second nodes.

12. The operational amplifier of claim 10 wherein said circuit for clamping the first and second nodes at a predetermined level with respect to the supply voltage and reference potential clamps the voltage at the first node at a voltage of 2V_BE below the supply voltage, and clamps the voltage at the second node at a voltage of 2V_BE above the reference potential.

13. The operational amplifier of claim 12 further comprising first and second current mirrors each having a mirror transistor to mirror an output current produced in response to said differential input signals on respective lines including said first and second nodes, and wherein said common-mode control circuit is in series with mirror transistors of said first and second current mirrors.

14. The operational amplifier of claim 12 wherein said high-swing output stage comprises a buffer stage connected to receive said first stage differential output signal and a pair of output transistors connected to produce an operational amplifier output.

15. The operational amplifier of claim 14 further comprising a class-AB mode biasing circuit for biasing said pair of output transistors.

16. The operational amplifier of claim 15 wherein said differential input circuit comprises a first pair of transistors of opposite conductivity type having control elements connected to receive one side of the differential input signal, and a second pair of transistors of opposite conductivity type having control elements connected to receive another side of the differential input signal.

17. The operational amplifier of claim 16 wherein said differential input circuit further comprises first and second current sources connected respectively between transistors of said first and second transistor pairs of a first conductivity type and a voltage supply, and between transistors of said first and second transistor pairs of a second conductivity type and a reference potential.

18. The operational amplifier of claim 17 wherein said operational amplifier is implemented with bipolar transistors.

19. The operational amplifier of claim 17 wherein said operational amplifier is implemented with MOS transistors.

20. A two-stage class-AB operational amplifier, comprising:

a differential input circuit adapted to receive a differential input signal to produce an amplified differential output signal on first and second nodes;

said differential input circuit having a common-mode control circuit that produces first and second common-mode control voltages on said first and second nodes, whereby said common-mode control voltages are combined with said amplified differential output signal on said first and second nodes to produce a first stage differential output signal;

and a high-swing output stage connected to receive the first stage differential output signal, said high-swing output stage including a buffer stage connected to receive said first stage differential output signal and a pair of output transistors connected to produce an operational amplifier output, and a class-AB mode biasing circuit for biasing said pair of output transistors.

21. The two-stage class-AB operational amplifier of claim 20 wherein the common-mode control voltages are multiplied with said differential input signal on said first and second nodes.

22. The two-stage class-AB operational amplifier of claim 20 further comprising first and second current mirrors each having a mirror transistor to mirror an output current produced in response to said differential input signals on respective lines including said first and second nodes, and wherein said common-mode control circuit is in series with mirror transistors of said first and second current mirrors.

23. The two-stage class-AB operational amplifier of claim 20 further comprising a circuit for clamping the first and second nodes at a predetermined level with respect to the supply voltage and reference potential;

24. The two-stage class-AB operational amplifier of claim 23 wherein said circuit for clamping the first and second nodes at a predetermined level with respect to the supply voltage and reference potential clamps the voltage at the first node at a voltage of 2V_BE below the supply voltage, and clamps the voltage at the second node at a voltage of 2V_BE above the reference potential.

25. The two-stage class-AB operational amplifier of claim 20 wherein said differential input circuit comprises a first pair of transistors of opposite conductivity type having control elements connected to receive one side of the differential input signal, and a second pair of transistors of opposite conductivity type having control elements connected to receive another side of the differential input signal.

26. The two-stage class-AB operational amplifier of claim 25 wherein said differential input circuit further comprises first and second current sources connected respectively between transistors of said first and second transistor pairs of a first conductivity type and a voltage supply, and between transistors of said first and second transistor pairs of a second conductivity type and a reference potential.

27. The two-stage class-AB operational amplifier of claim 20 wherein said operational amplifier is implemented with bipolar transistors.

28. The two-stage class-AB operational amplifier of claim 20 wherein said operational amplifier is implemented with MOS transistors.