Apparatus and method for compensating a radar's sensitivity timing control circuit

• US 5,293,325 A
• Filed: 11/22/1991
• Issued: 03/08/1994
• Est. Priority Date: 11/22/1991
• Status: Expired due to Fees

• Current Assignee: Alliedsignal Inc. (Honeywell International Inc.)
• Original Assignee: Alliedsignal Inc. (Honeywell International Inc.)
• Inventors: Roos, Mark G.
• Primary Examiner(s): Harvey, Jack B.
• Assistant Examiner(s): Wachsman, Hal D.
• Application Number:
  US07/797,511
• Time in Patent Office: 837 Days
• Field of Search: 364/571.01, 364/571.02, 364/571.04-571.08, 364/569, 342/91, 342/92, 342/174, 342/205, 307/264, 307/494, 307/491, 307/493, 330/52, 330/193, 330/129
• US Class Current: 702/89
• CPC Class Codes: G01S 7/34 Gain of receiver varied automatically during pulse-recurrence period, e.g. anti-clutter gain control
• CPC Class Codes: G01S 7/4021 of receivers

Abstract

The signal that controls the gain of a sensitivity timing control (STC) circuit is slimmed with a gain correction signal to compensate for gain variations introduced by items such as variations in the parameters of electronic components. A known test signal is injected into the STC circuit and the resulting output signal is measured. The amplitude of the gain correction signal is determined based on the difference between the desired output signal amplitude and the measured output signal amplitude.

Claims

1. An apparatus for correcting a gain of a sensitivity timing control circuit, comprising:

(a) test signal generation means for providing an input test signal to the sensitivity timing control circuit so that an output signal having a given amplitude results;

(b) computing means for calculating an amplitude of a gain correction signal using said given output signal amplitude, wherein said computing means sets a present gain correction signal amplitude to a value of substantially zero, calculates a difference between a desired output signal amplitude and said given output signal amplitude, calculates a new gain correction signal amplitude, and averages a stored gain correction signal amplitude and said new gain correction signal amplitude to calculate said gain correction signal amplitude; and

(c) summing means for modifying the gain of the sensitivity timing control circuit using said gain correction signal.

2. The apparatus of claim 1, wherein said computing means calculates an average gain correction signal amplitude using the equation ##EQU5## where D_ave is said average gain correction signal amplitude, D_j is one of a plurality of grain correction signal amplitudes calculated during one PRT (Pulse Repetition Time) m is a first number equal to the total number of gain correction signal amplitudes in said plurality of gain correction signal amplitudes, and n is a second number equal to the total number of PRTs over which said average gain correction signal amplitude is calculated.

3. The apparatus of claim 1, wherein said test signal generation means comprises a calibrated noise diode.

4. The apparatus of claim 1, further comprising detector means for converting said given amplitude output signal into a DC output signal.

5. The apparatus of claim 4, further comprising analog to digital converter means for converting said DC output signal into a digital output signal.

6. The apparatus of claim 5, further comprising digital to analog converter means for converting a digital gain correction signal into said gain correction signal.

7. The apparatus of claim 6, wherein said test signal generation means comprises a calibrated noise diode.

8. A sensitivity timing control circuit having gain compensation, comprising:

(a) amplifier means for variably amplifying an input signal in response to a corrected gain signal;

(b) memory means for storing a plurality of gain values;

(c) first digital to analog converter means for converting a gain value into an analog gain signal;

(d) test signal generation means for providing an input test signal to said amplifier means so that an output signal having a given amplitude results;

(e) computing means for calculating an amplitude of a gain correction signal using said given output signal amplitude, wherein said computing means sets a present gain correction signal amplitude to a value of substantially zero, calculates a difference between a desired output signal amplitude and said given output signal amplitude, calculates a new gain correction signal amplitude, and averages a stored gain correction signal amplitude and said new gain correction signal amplitude to calculate said gain correction signal amplitude; and

(f) summing means for summing said gain correction signal and said analog gain signal to produce said corrected gain signal.

9. The apparatus of claim 8, wherein said computing means calculates an average gain correction signal amplitude using the equation ##EQU6## where D_ave is said average gain correction signal amplitude, D_j is one of a plurality of grain correction signal amplitudes calculated during one PRT (Pulse Repetition Time), m is a first number equal to the total number of gain correction signal amplitudes in said plurality of gain correction signal amplitudes, and n is a second number equal to the total number of PRTs over which said average gain correction signal amplitude is calculated.

10. The apparatus of claim 8, wherein said test signal generation means comprises a calibrated noise diode.

11. The apparatus of claim 8, further comprising detector means for converting said given amplitude output signal into a DC output signal.

12. The apparatus of claim 11, further comprising analog to digital converter means for converting said DC output signal into a digital output signal.

13. The apparatus of claim 12, further comprising second digital to analog converter means for converting a digital gain correction signal into said gain correction signal.

14. A sensitivity timing control circuit having gain compensation, comprising:

(a) amplifier means for variably amplifying an input signal in response to an analog gain signal;

(b) memory means for storing a plurality of current digital gain values;

(c) digital to analog converter means for converting a current digital gain value into an analog gain signal;

(d) test signal generation means for providing an input test signal to said amplifier means so that an output signal having a given amplitude results, said test signal generation means having a calibrated noise diode;

(e) detector means for converting said output signal into a DC output signal;

(f) analog to digital converter means for converting said DC output signal into a digital output signal; and

(g) computing means for producing a new digital gain value by using said digital output signal to calculate a difference between said given output signal amplitude and a desired output signal amplitude to produce a digital gain correction value, and by summing said digital gain correction value and a current digital gain value.