Network adapter with high throughput data transfer circuit to optimize network data transfers, with host receive ring resource monitoring and reporting

• US 5,293,487 A
• Filed: 12/27/1991
• Issued: 03/08/1994
• Est. Priority Date: 12/27/1991
• Status: Expired due to Term

• Current Assignee: Enterasys Networks Incorporated (Extreme Networks, Inc.)
• Original Assignee: Digital Equipment Corporation (HP Inc.)
• Inventors: Sullivan, Edward T., Rege, Satish L., Kempf, Mark F., Russo, Andrew P.
• Primary Examiner(s): RICHARDSON, ROBERT
• Application Number:
  US07/815,008
• Time in Patent Office: 802 Days
• Field of Search: 364/DIG. 1, 364/DIG. 2, 395/200, 395/275, 395/250, 370/60, 370/85.1, 370/85.2, 370/94.1
• US Class Current: 709/250
• CPC Class Codes: G06F 13/128 for dedicated transfers to a network for protocol converters G06F13/387
• CPC Class Codes: H04L 12/417 with deterministic access, e.g. token passing
• CPC Class Codes: H04L 41/24 using dedicated network management hardware
• CPC Class Codes: H04L 9/40 Network security protocols

Abstract

A network adapter with high throughput data transfer circuit to optimize network data transfers, with host receive ring resource monitoring and reporting is disclosed. Time critical network data is transferred between the network adapter and the host computer system by means of a high throughput data transfer circuit. The high throughput data transfer circuit is designed to provide throughput equal to the bandwidth of a high speed local area network such as the Fiber Distributed Data Interconnect. The high throughput data transfer circuit will inform the local intelligence of the network adapter if the network adapter has used up all host computer system memory allocated for storing data received from the network. Adapter management data is transferred between the network adapter and the host computer system local area network through a lower throughput data transfer circuit.

Claims

1. A network adapter for data transfer between a host computer system and a computer network, said network adapter coupled with both said host computer system and said computer network, said host computer system having a host memory, and said host memory containing one or more adapter manager command buffers, comprising:

a packet memory, containing one or more data packets received by said network adapter from said computer network;

a higher throughput data transfer circuit, coupled with said packet memory, for transferring said one or more data packets received from said computer network, from said packet memory to said host memory;

an adapter management subsystem, responsive to said adapter management command buffers in said host memory, for processing said adapter management command buffers, and for generating command responses in response to said adapter management command buffers; and

a lower throughput data transfer circuit, coupled with said adapter management subsystem, and responsive to said adapter management subsystem, for transferring said adapter management command buffers from said host memory to said adapter management subsystem and for transferring said command responses from said adapter management subsystem to said host memory.

2. The network adapter as in claim 1, wherein said higher throughput data transfer circuit further comprises:

a first means for determining whether a host receive buffer in said host memory is available for storage of packet data from said packet memory;

a second means, responsive to said first means, for notifying said adapter management subsystem when said host receive buffer is not available.

3. The network adapter as in claim 2 wherein said higher throughput data transfer circuit further comprises:

a first state machine means, responsive to the contents of a next transmit pointer in said higher throughput data transfer circuit, for reading a ring entry contained in a transmit ring located in said host memory pointed to by said next transmit pointer, said entry containing an ownership bit, a buffer address field, a buffer length field, and a transmit completion code field, and outputting the buffer length and buffer address from said buffer length field and said buffer address field;

a second state machine means for receiving said buffer address and said buffer length output from said first state machine, moving buffer data indicated by said buffer address and said buffer length into said packet memory, and outputing a transmit completion code;

a third state machine means for receiving said transmit completion code output from said second state machine, writing said transmit completion code to said transmit ring entry transmit completion code field, and setting the value of said next transmit pointer to the next sequential ring entry in said transmit ring;

a fourth state machine means responsive to the contents of a next receive pointer in said higher throughput data transfer circuit, for reading a ring entry contained in a receive ring located in said host memory pointed to by said next receive pointer, said entry containing an ownership bit, a buffer address field, a buffer length field, and a receive completion code field, and outputing the buffer length and buffer address from said buffer length field and said buffer address field;

a fifth state machine means for receiving said buffer address and said buffer length output from said fourth state machine, and moving packet data from said packet memory into said host memory at memory locations indicated by said buffer address and said buffer length, and outputing a receive completion code; and

a sixth state machine means for receiving said receive completion code output from said fifth state machine, writing said receive completion code to said receive ring entry receive completion code field, and setting the value of said next receive pointer to the next sequential ring entry in said receive ring.

4. The network adapter as in claim 3, wherein said lower speed data transfer circuit further comprises:

a first state machine means, responsive to address and length inputs, for reading and writing said host memory, in the case of reading said host memory outputing the data read, and in the case of writing said host memory outputing a completion status of the write operation;

a second process means, responsive to said adapter management subsystem, for providing address and length inputs to said first means, receiving said data or completion code outputs from said first means, and outputing said data or completion code to said adapter management subsystem.

5. The network adapter as in claim 4, wherein all said state machine means are implemented in a single application specific integrated circuit (ASIC).

6. The network adapter as in claim 5, wherein said higher speed data transfer circuit further comprises:

a next transmit pointer containing the address of the next transmit ring entry to be processed; and

a next receive pointer containing the address of the next receive ring entry to be processed.

7. The network adapter as in claim 6, wherein said adapter management subsystem further comprises:

a next command pointer containing the address of a next command ring entry to be processed; and

a next unsolicited pointer containing the address of a next unsolicited ring entry to be processed.

8. The network adapter as in claim 2, wherein said adapter management subsystem includes a host notification means, responsive to said second means for notifying said adapter management subsystem when said host receive buffer is not available, for notifying said host computer system when said receive buffer is not available.

9. The network adapter as in claim 8, wherein said host notification means includes a means for writing an entry into an unsolicited ring in said host memory.

10. The network adapter as in claim 1, wherein said one or more adapter management command buffers includes an adapter manager command requesting adapter initialization.

11. The network adapter as in claim 1, wherein said one or more adapter management command buffers includes an adapter manager command requesting a diagnostic function.

12. The network adapter as in claim 1, wherein said one or more adapter management command buffers includes an adapter manager command requesting a network management function.

13. A network adapter coupled with a host computer and a high speed local area network, comprising:

a first data transfer circuit providing throughput equal to that of said high speed local area network, for transferring data packets directly between a memory in said host computer system and said high speed local area network; and

a second data transfer circuit providing a lower throughput, for transferring data related to operations performed internally within said network adapter.

14. The network adapter as in claim 13, wherein said data related to operations performed internally within said network adapter includes an adapter manager command issued by said host computer requesting an initialization of said network adapter.

15. The network adapter as in claim 13, wherein said data related to operations performed within said network adapter includes an adapter management command issued by said host computer requesting a diagnostic function.

16. The network adapter as in claim 13, wherein said data related to operations performed within said network adapter includes an adapter management command issued by said host computer requesting a network management function.

17. The network adapter as in claim 16, further comprising:

an adapter management subsystem for performing said operations performed within said network adapter, and for generating a first response to said adapter management command issued by said host computer requesting a network management function, and for generating a second response to said adapter manager command requesting a diagnostic function, and for initializing said network adapter in response to said command requesting initialization of said network adapter; and

wherein said data related to operations performed within said network adapter includes said first response and said second response generated by said adapter management subsystem.

18. A system for passing data between a high speed local area network and a host computer comprising:

a network adapter, coupled with said host computer system and said high speed local area network, said network adapter including a packet memory for storing packets received from said high speed local area network and an adapter management subsystem for generating responses to adapter manager commands received from said host computer system;

a host memory, having a transmit ring containing transmit ring entries indicating transmit buffers, said transmit buffers containing packets to be transmitted onto said high speed local area network, said host memory further containing a receive ring containing receive ring entries indicating receive buffers, said receive buffers for storing data received from said high speed local area network, said host memory also containing a command ring containing command ring entries indicating command buffers, said command buffers containing adapter manager commands for said network adapter, said host memory also containing an unsolicited ring containing unsolicited ring entries, said unsolicited ring entries containing unsolicited information generated by said network adapter;

a high throughput data transfer circuit for transferring said transmit buffers from said host memory into said packet memory in said network adapter, and for transferring a packet received from said high speed local area network by said network adapter from said packet memory in said network adapter into one of said receive buffers in said host memory; and

a low throughput data transfer circuit for transferring said adapter manager commands from said host memory to said adapter management subsystem within said network adapter, and for transferring said responses to adapter manager commands received from said host computer system from said adapter management subsystem into said unsolicited ring entries in said host memory.