Multiplication, division and square root extraction apparatus

• US 5,293,558 A
• Filed: 07/03/1990
• Issued: 03/08/1994
• Est. Priority Date: 11/04/1988
• Status: Expired due to Fees

• Current Assignee: Hitachi Engineering Co.,Ltd (Hitachi, Ltd.), Hitachi, Ltd.
• Original Assignee: Hitachi Engineering Co.,Ltd (Hitachi, Ltd.), Hitachi, Ltd.
• Inventors: Nakagawa, Norio, Morinaga, Shigeki, Nakamikawa, Tetsuaki, Asai, Takeshi, Watabe, Mitsuru, Kashiwagi, Yugo, Kida, Hiroyuki, Narita, Masahisa, Kaziwara, Hisashi, Kawasaki, Shunpei, Tatezaki, Junichi
• Primary Examiner(s): Mai, Tan V.
• Application Number:
  US07/536,565
• Time in Patent Office: 1,344 Days
• Field of Search: 364/752, 364/754, 364/761
• US Class Current: 708/605
• CPC Class Codes: G06F 2207/3816 Accepting numbers of variable word length
• CPC Class Codes: G06F 2207/5355 Using iterative approximation not using digit recurrence, e.g. Newton Raphson or Goldschmidt
• CPC Class Codes: G06F 2207/5356 Via reciprocal, i.e. calculate reciprocal only, or calculate reciprocal first and then the quotient from the reciprocal and the numerator
• CPC Class Codes: G06F 7/4873 Dividing
• CPC Class Codes: G06F 7/49957 Implementation of IEEE-754 Standard
• CPC Class Codes: G06F 7/535 Dividing only
• CPC Class Codes: G06F 7/5525 Roots or inverse roots of single operands
• CPC Class Codes: G06F 7/57 Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations G06F7/49, G06F7/491 take precedence

Abstract

A multiplication, division and square root extraction apparatus which calculates the solutions to addition, division and square root extraction functions by approximation using iteration has a multiplier, an adder-subtracter and a shifter of prescribed bit width connected to a bus. Iteration is conducted by inputting the output of the multiplier to the adder-subtracter or the shifter and returning the result to the input of the multiplier via the bus. A shifter and an arithmetic and logic unit connected to a second bus connected to the aforesaid bus via a switch have a greater bit width than the prescribed bit width and are used for large scale calculations, thus preventing a reduction in processing speed.

Claims

1. A multiplication, division and square root extraction apparatus which, for carrying out multiplication, division and square root extraction calculations, calculates approximate solutions of multiplication, division and square root extraction functions by iteration through repeated multiplication, addition and subtraction, said apparatus comprising:

a multiplier of prescribed bit width, having first and second inputs and an output, for carrying out multiplication between respective values of a prescribed number of bits received at said first and second inputs, and for supplying the product of said values at said output;

a subtractor of prescribed bit width connected to said output of said multiplier for subtracting said product from a prescribed value and for outputting the result of the subtraction;

a data transfer device, connected to said output of said subtractor and said first and second inputs of said multiplier, for transferring said output of said subtractor to a selected one of said first and second inputs of said multiplier according to an iteration algorithm; and

a square root extraction approximation means for calculating a first product of a square of an approximate value and the number whose square root is to be obtained, subtracting said first product from a constant, calculating a second product of the result of the subtraction, the approximate value and another constant, and providing said second product for a subsequent approximation.

2. A multiplication, division and square root extraction apparatus which, for carrying out multiplication, division and square root extraction calculations, calculates approximate solutions of multiplication, division and square root extraction functions by iteration through repeated multiplication, addition and subtraction, said apparatus comprising:

a multiplier of prescribed bit width, having a first and second inputs and an output, for carrying out multiplication between respective values of a prescribed number of bits received at said first and second inputs, and for supplying the product of said values at said output;

a subtractor of prescribed bit width connected to said output of said multiplier for subtracting said product from a prescribed value and for outputting the result of the subtraction;

a data transfer device, connected to said output of said subtractor and said first and second inputs of said multiplier, for transferring said output of said subtractor to a selected one of said first and second inputs of said multiplier according to an iteration algorithm;

shift means, having a second bit width greater than the prescribed bit width of said multiplier, for shifting a result produced by said multiplier;

arithmetic and logic means, having a second bit width connected to said shift means, for processing an output o the sift means and another result produced by said multiplier; and

a second data transfer device connected to said data transfer device through a switch means, also connected to said shift means and said arithmetic and logic means, for transferring a product from said multiplier to said shift means and/or said arithmetic and logic means, and a result of said arithmetic and logic means to said multiplier.

3. A multiplication, division and square root extraction apparatus according to claim 2, wherein the shift means has rounding-off means of shifting data by one or more bits and rounding off the shifted out data.

4. A multiplication, division and square root extraction apparatus according to claim 2, wherein the processing by the shift means and the arithmetic and logic means and the processing by the multiplier and the subtracter are conducted in parallel during a period when the first and second data transfer means are separated by the switch.

5. A multiplication, division and square root extraction apparatus according to claim 4, wherein the multiplier carries out a plurality of multiplications by pipeline processing.