Multi-state flash EEPROM system using incremental programing and erasing methods

• US 5,293,560 A
• Filed: 11/03/1992
• Issued: 03/08/1994
• Est. Priority Date: 06/08/1988
• Status: Expired due to Term

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Eliyahou Harari
• Inventors: Harari, Eliyahou
• Primary Examiner(s): Gossage, Glenn
• Application Number:
  US07/970,949
• Time in Patent Office: 490 Days
• Field of Search: 365/184, 365/185, 365/189.07, 365/218, 365/236, 365/230.03
• US Class Current: 365/185.03
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5635 Erasing circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0425 comprising cells containing a merged floating gate and select transistor
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 16/3495 Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically
• CPC Class Codes: G11C 2211/5613 Multilevel memory cell with additional gates, not being floating or control gates
• CPC Class Codes: G11C 2211/5631 Concurrent multilevel reading of more than one cell
• CPC Class Codes: G11C 2211/5634 Reference cells
• CPC Class Codes: G11C 2211/5644 Multilevel memory comprising counting devices
• CPC Class Codes: G11C 29/00 Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
• CPC Class Codes: G11C 29/765 in solid state disks
• CPC Class Codes: G11C 29/82 for EEPROMs
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H01L 29/7885 Hot carrier injection from the channel
• CPC Class Codes: H10B 41/00 Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A memory system made up of electrically programmable read only memory (EPROM) or flash electrically erasable and programmable read only memory (EEPROM) cells. An intelligent programming technique allows each memory cell to store more than the usual one bit of information. More than one bit is stored in a cell by establishing more than two distinct threshold states into which the cell is programmed. A series of pulses of increasing voltage is applied to each addressed memory cell during its programming, the state of the cell being read in between pulses. The pulses are terminated upon the addressed cell reaching its desired state or a preset maximum number of pulses has been reached. An intelligent erase algorithm prolongs the useful life of the memory cells. A series of pulses is also applied to a block of cells being erased, the state of at least a sample number of cells being read in between pulses. The erasing process is stopped when the cells being read are determined to have reached a fully erased state or one of a number of other conditions has occurred. Use of these various features provides a memory having a very high storage density and a long life, making it particularly useful as a solid state memory in place of magnetic disk storage devices in computer systems.

Claims

1. An electrically erasable programmable read only memory (EEPROM) system, comprising:

a semiconductor substrate including an array of a plurality of storage cells arranged in rows and columns across said substrate, each cell including;

a source region and a drain region formed in said substrate with a channel therebetween,

a floating gate positioned over a first portion of the channel in a manner that a level of charge on the floating gate establishes a threshold level of a first transistor, thereby affecting a level of conductance through the first channel portion between the source and drain regions,

a control gate positioned over a second portion of the channel adjacent the first channel portion, thereby forming a second transistor connected in series with the first transistor, said control gate also extending across the floating gate in a manner that a level of electrical potential on the control gate affects the level of conductance of both of the first and second transistors through the respective first and second portions of the channel between the source and drain regions, and

an erase gate positioned adjacent said floating gate;

programming means connectable to a selected cell within the array of cells for applying voltages to the first transistor of the selected cell to increase an electron charge on its floating gate, thereby to alter the threshold level of the first transistor of the selected cell,

reading means connectable to an addressed cell within the array of cells for detecting a level of conductance between the source and drain regions of the addressed cell in response to a predetermined voltage being applied across the source and drain regions of the addressed cell and a predetermined potential level being applied to the control gate of the addressed cell,

erasing means connectable to erase gates of storage cells within one of a plurality of distinct blocks of cells of the array for simultaneously removing electrical charge from the floating gates of the cells within said one block that is sufficient to drive the threshold levels of the first transistors of said one block of cells to an erased level, each of said plurality of blocks including cells within multiple rows and multiple columns,

wherein said reading means includes means for discriminating between a plurality of more than two predetermined threshold levels of the first transistor of the addressed cell, at least one of said more than two programmable threshold levels having a net positive charge on the floating gate of the first transistor of the addressed cell, each cell having a plurality of storage states more than two, and

said programming means includes means for applying a sequence of programming voltage pulses to the first transistor of the selected cell to increase an electron charge on its floating gate from said erased level until at least either (a) a threshold level detected by said reading means in the first transistor of the selected cell is substantially equal to a desired one of the more than two threshold levels, or (b) a preset number of pulses has been applied.

2. The EEPROM system of claim 1 further comprising means for accumulating a count of the number of times that said plurality of storage cells has been erased.

3. The EEPROM system of claim 1 further comprising means provided as part of each of said distinct blocks of memory cells for maintaining a count of the number of times the associated block of cells has been erased.

4. The EEPROM system of claim 1 wherein said reading means additionally includes at least one differential sense amplifier coupled to the drain of the addressed cell, wherein more than two reference levels are provided to said differential sense amplifier, thereby to establish the more than two predetermined threshold levels for individual cells of said array of cells.

5. The EEPROM system of claim 1 wherein the first transistor of each of said memory array cells is characterized by a given natural threshold voltage level, and wherein at least two of said more than two predetermined threshold levels result from a threshold voltage of the first transistor of the selected cell being reduced by a charge on its floating gate to a level that is less than said natural threshold voltage level.

6. The EEPROM system of claim 1 wherein said pulse applying means includes means for limiting a magnitude of each of said sequence of voltage pulses to a value that is less than that which shifts the threshold level of the first transistor of the selected cell one-half a difference between adjacent of said more than two predetermined threshold levels.

7. The EEPROM system of claim 1 wherein said second transistor is characterized by a fixed threshold level greater than a native threshold level of the first transistor.

8. The EEPROM system of claim 1 wherein a majority of said plurality of more than two predetermined threshold levels have a net positive charge on the floating gate of the first transistor of the addressed cell.

9. The EEPROM system of claim 1 wherein all of said plurality of more than two predetermined threshold levels have a net positive charge on the floating gate of the first transistor of the addressed cell.

10. The EEPROM system of claim 1 wherein the discriminating means of said reading means includes means for discriminating between exactly three predetermined threshold levels.

11. The EEPROM system of claim 1 wherein the discriminating means of said reading means includes means for discriminating between exactly four predetermined threshold levels.

12. The EEPROM system of claim 1 wherein the reading means includes means for detecting a voltage level across the source and drain regions of the addressed cell, thereby to detect the level of conductance between said source and drain.

13. The EEPROM system of claim 1 wherein the reading means includes means for detecting a level of current flowing through the addressed cell between the source and drain regions thereof, thereby to detect the level of conductance between said source and drain.

14. The EEPROM system of claim 13 wherein the reading means additionally includes:

a plurality of reference current sources corresponding respectively to said plurality of more than two predetermined threshold levels, and

means for simultaneously comparing the current flowing through the addressed cell with each of the reference current sources.

15. The EEPROM system of claim 1 wherein said erasing means includes means for repeating a cycle of applying an erase voltage in a short erase pulse to the cells within the distinct block being erased and then causing said reading means to determine the threshold level of at least some of the cells within that block, the voltage level of an initial erase pulse being insufficient to fully erase the cells of the distinct block being erased and increasing an incremental amount from pulse to pulse.

16. The EEPROM system of claim 15 wherein said erasing means includes means for repeating said erase cycle only until the first occurrence of any one of the following conditions:

(1) the threshold level of all of said at least some of the cells of the distinct block has reached said erased level;

or

(2) a preset maximum number of said erase cycles has occurred;

or

(3) a predetermined maximum voltage of the erase pulse has been reached;

or

(4) the number of said at least some of the cells of the distinct block which have not reached said erased level has declined below a predetermined acceptable number of cells.

17. The EEPROM system of claim 15 wherein said erasing means includes means for incrementing the voltage level of each respective erase voltage pulse after the initial pulse by an amount of the voltage of the initial pulse plus a fixed voltage increment times the number of the respective pulse in a sequence after the first pulse.

18. An electrically erasable programmable read only memory (EEPROM) system, comprising:

a semiconductor substrate including an array of a plurality of storage cells arranged in rows and columns across said substrate, said plurality of cells being formed to individually include;

a source region and a drain region formed in a surface of said substrate with a channel therebetween,

a floating gate positioned over a first portion of the channel and separated from said substrate surface by a first dielectric layer in a manner that a level of charge on the floating gate controls a level of conductance through the first channel portion, thereby forming a first transistor whose threshold level is controlled by the level of charge on the floating gate,

a control gate positioned over a second portion of the channel adjacent the first channel portion and separated from said substrate surface by a second dielectric layer, thereby forming a second transistor connected in series with the first transistor, said control gate also extending across the floating gate in a manner that a level of electrical potential on the control gate affects the level of conductance of both of the first and second transistors through the respective first and second portions of the channel between the source and drain regions, and

an erase gate positioned adjacent said floating gate and separated therefrom by a third dielectric layer,

reading means connectable to an addressed cell within the array of cells for detecting a level of conductance between the source and drain regions of the addressed cell, said reading means includes means for discriminating between a plurality of more than two predetermined threshold levels of the first transistor of the addressed cell wherein at least one of said predetermined threshold levels results from a net positive charge on the floating gate of the first transistor of the addressed cell, the cells of the array having a predetermined number of storage states more than two,

erasing means simultaneously connectable to the erase gates of storage cells within one of a plurality of distinct blocks of cells in multiple rows and columns of the array for simultaneously reducing an electron charge from the floating gates of cells within said one block by applying thereto a sequence of pulses of increasing magnitude until at least either (a) threshold levels detected by said reading means between said erase pulses in at least a preset proportion of the cells of said one block reach an erased level, or (b) a preset maximum number of erase pulses have occurred, and

programming means connectable to a selected cell within the array of cells for increasing an electron charge on its floating gate by applying a sequence of programming pulses to the selected cell until at least either (a) a threshold level detected by said reading means between said programming pulses in the first transistor of the selected cell is raised from said erased level to substantially equal a desired one of said more than two predetermined threshold levels, or (b) a preset maximum number of programming pulses has been applied.

19. The EEPROM system of claim 18 wherein said erasing means includes means for incrementing the magnitude of each respective erase pulse after the initial pulse by an amount of the magnitude of the initial pulse plus a fixed magnitude increment times the number of the respective pulse in a sequence after the first pulse.

20. The EEPROM system of claim 18 wherein said programming means includes means for limiting a magnitude of each of said sequence of programming pulses to a value that is less than that which shifts the threshold level of the first transistor of the selected cell one-half a difference between adjacent threshold levels of said more than two predetermined threshold levels.

21. The EEPROM system of claim 18 wherein said second transistor is characterized by a fixed threshold level greater than a natural threshold level of the first transistor.

22. The EEPROM system of claim 18 wherein at least two of said predetermined threshold levels are lower than a natural threshold level of the first transistor of the addressed cell.

23. The EEPROM system of claim 18 wherein a majority of said plurality of more than two predetermined threshold levels have a net positive charge on the floating gate of the first transistor of the addressed cell.

24. The EEPROM system of claim 18 wherein all of said plurality of more than two predetermined threshold levels have a net positive charge on the floating gate of the first transistor of the addressed cell.

25. The EEPROM system of claim 18 wherein said reading means includes means for discriminating between exactly three predetermined threshold levels.

26. The EEPROM system of claim 18 wherein said reading means includes means for discriminating between exactly four predetermined threshold levels.

27. The EEPROM system of claim 18 wherein said reading means includes:

a plurality of reference current sources corresponding respectively to said plurality of more than two predetermined threshold levels, and

means for simultaneously comparing current flowing through the addressed cell with each of the reference current sources, thereby to determine a storage state of the addressed cell.