Data processing system which generates a waveform with improved pulse width resolution
First Claim
1. A data processing system, comprising:
- a high resolution counter, said high resolution counter receiving a clock signal having a predetermined period and a predetermined half-period, the predetermined half-period being equal to one-half the predetermined period;
wherein said high resolution counter comprises;
counter means for counting, said counter means having a count value, the count value having a first portion and a second portion;
compare means for comparing, said compare means being coupled to said counter means, said compare means for receiving a duty control value, the duty control value having a first portion and a second portion, said compare means for comparing the first portion of the duty control value to the first portion of the count value; and
waveform means for generating an output signal, said waveform means being coupled to said compare means, if the duty control value is an even value, then the output signal transitions from a first logic state to a second logic state when the first portion of the duty control value matches the first portion of the count value, but if the duty control value is an odd value, then the output signal transitions from the first logic state to the second logic state one predetermined half-period after the first portion of the duty control value matches the first portion of the count value.
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Accused Products
Abstract
A data processing system (10) capable of generating an output waveform (22) that has enhanced pulse width resolution. In one form, the system uses a counter (34) which is incremented by an input clock (20) running at an operating frequency of the system. Instead of incrementing the counter (34) by one, the counter (34) is incremented by a power of two so that the counter (34) appears to be counting a power of two faster. However, in order to increase the effective resolution of the counter (34), the second edge of the output waveform (22) must be correctly adjusted depending on the desired duty cycle and period. The end result is a counter (34) that can produce a power of two greater resolution while still using the operating frequency of the system as an input clock (20).
55 Citations
20 Claims
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1. A data processing system, comprising:
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a high resolution counter, said high resolution counter receiving a clock signal having a predetermined period and a predetermined half-period, the predetermined half-period being equal to one-half the predetermined period; wherein said high resolution counter comprises; counter means for counting, said counter means having a count value, the count value having a first portion and a second portion; compare means for comparing, said compare means being coupled to said counter means, said compare means for receiving a duty control value, the duty control value having a first portion and a second portion, said compare means for comparing the first portion of the duty control value to the first portion of the count value; and waveform means for generating an output signal, said waveform means being coupled to said compare means, if the duty control value is an even value, then the output signal transitions from a first logic state to a second logic state when the first portion of the duty control value matches the first portion of the count value, but if the duty control value is an odd value, then the output signal transitions from the first logic state to the second logic state one predetermined half-period after the first portion of the duty control value matches the first portion of the count value. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A method of using a clock signal to generate a signal waveform having improved pulse width resolution, the clock signal having a predetermined period and a predetermined half-period, the predetermined half-period being equal to one-half the predetermined period, the method comprising the steps of:
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receiving the clock signal; receiving a duty control value; incrementing/decrementing a count value by 2N, where N is an integer greater than or equal to zero; comparing at least a portion of the duty control value to at least a portion of the count value; asserting a match signal when the at least a portion of the duty control value matches the at least a portion of the count value; if the duty control value is an integer multiple of 2N, transitioning the signal waveform from a first logic state to a second logic state when the match signal is asserted; and if the duty control value is not an integer multiple of 2N and if the duty control value equals 2N +1, transitioning the signal waveform from a first logic state to a second logic state one predetermined half-period after the match signal is asserted. - View Dependent Claims (11, 12, 13, 14, 15, 16)
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17. In a data processing system having a clock signal, the clock signal having a predetermined period and a predetermined half-period, the predetermined half-period being equal to one-half the predetermined period, a method of generating a signal waveform using the clock signal, the method comprising the steps of:
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storing a count value, the count value having a least significant bit and a plurality of most significant bits; receiving the clock signal; receiving a duty control value, the duty control value having a least significant bit and a plurality of most significant bits; selecting one of a lower resolution mode and a higher resolution mode; if the lower resolution mode has been selected, performing the following steps; (a) incrementing/decrementing the count value by ones using the clock signal; (b) comparing the duty control value and the count value; and (c) transitioning the signal waveform from a first logic state to a second logic state when the duty control value matches the count value; and if the higher resolution mode has been selected, performing the following steps; (i) incrementing/decrementing the counter by twos using the clock signal; (ii) comparing the plurality of most significant bits of the duty control value to the plurality of most significant bits of the count value; (iii) if the duty control value is an even value, transitioning the signal waveform from the first logic state to the second logic state when the plurality of most significant bits of the duty control value matches the plurality of most significant bits of the count value; and (iv) if the duty control value is an odd value, transitioning the signal waveform from a first logic state to a second logic state one predetermined half-period after the plurality of most significant bits of the duty control value matches the plurality of most significant bits of the count value. - View Dependent Claims (18, 19, 20)
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Specification