Semiconductor device having identification region for carrying out failure analysis

• US 5,294,812 A
• Filed: 03/26/1993
• Issued: 03/15/1994
• Est. Priority Date: 09/14/1990
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Asoh, Syoichi, Hashimoto, Kazuhiko, Matsui, Masataka
• Primary Examiner(s): Pascal, Robert J.
• Assistant Examiner(s): Ratliff, Reginald A.
• Application Number:
  US08/038,063
• Time in Patent Office: 354 Days
• Field of Search: 357/52, 357/65, 257/65, 257/297, 257/289, 257/786, 257/773, 257/213, 257/206, 257/48
• US Class Current: 257/65
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: H01L 2223/54406 comprising alphanumeric information
• CPC Class Codes: H01L 2223/54413 comprising digital information, e.g. bar codes, data matrix
• CPC Class Codes: H01L 2223/54433 containing identification or tracking information
• CPC Class Codes: H01L 2223/5444 for electrical read out
• CPC Class Codes: H01L 2223/54473 for use after dicing
• CPC Class Codes: H01L 2223/5448 Located on chip prior to dicing and remaining on chip after dicing
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor device capable of performing a failure analysis includes a semiconductor substrate having a plurality of circuit elements, and an identification region provided above the semiconductor substrate so as to record identification information such as position information within wafers, information for wafer numbers, etc. The identification information is given by binary coded patterns, fused patterns of fuse elements, etc.

Claims

1. A semiconductor device including a semiconductor substrate having a plurality of circuit elements, an insulating film covering a surface of the semiconductor substrate, and a passivation film covering the insulating film, the semiconductor device further comprising:

an identification region, located at a corner of the semiconductor substrate, including a plurality of pattern segments provided on the insulating film, the plurality of pattern segments being covered with the passivation film, wherein

a portion of at least one of the plurality of pattern segments is removed along with the insulating film and the passivation film to provide an identification pattern for providing identification information regarding the semiconductor device.

2. The semiconductor device according to claim 1, wherein the identification pattern provides coded information.

3. The semiconductor device according to claim 1, wherein the plurality of pattern segments are formed in a matrix-shaped pattern.

4. The semiconductor device according to claim 1, wherein the plurality of pattern segments comprise a material selected from polysilicon, a metal, metal silicide and an insulator.

5. The semiconductor device according to claim 1, wherein each of the plurality of pattern segments is rectangular.

6. The semiconductor device according to claim 1, wherein the portion of the at least one of the plurality of pattern segments is removed by a laser beam.

7. A semiconductor device including a semiconductor substrate having a plurality of circuit elements, an insulating film covering a surface of the semiconductor substrate, and a passivation film covering the insulating film, the semiconductor device further comprising:

an identification region, located at a corner of the semiconductor substrate, including a layer for providing an identification pattern, the layer being formed on a portion of the insulating film and covered with the passivation film, wherein

the layer is patterned from the passivation film to form the identification pattern for providing identification information regarding the semiconductor device.

8. The semiconductor device according to claim 7, wherein the identification pattern is a combination of different characters.

9. The semiconductor device according to claim 7, wherein the identification pattern is a combination of different numerals.

10. The semiconductor device according to claim 7, wherein the layer comprises a material selected from polysilicon, a metal, metal silicide and an insulator.

11. The semiconductor device according to claim 7, wherein the layer is patterned by a laser beam.

12. A semiconductor device including a semiconductor substrate having a plurality of circuit elements, an insulating film covering a surface of the semiconductor substrate, and a passivation film covering the insulating film, the semiconductor device further comprising:

an identification region, located at a corner of the passivation film, including an identification pattern of identification information regarding the semiconductor device.

13. The semiconductor device according to claim 12, wherein the identification pattern comprises a concave pattern formed in the passivation film.

14. The semiconductor device according to claim 12, wherein the identification pattern comprises a convex pattern formed on the passivation film.

15. A semiconductor device including a redundancy circuit and an enable latch having fuse means for activating the redundancy circuit, the semiconductor device further comprising:

an identification circuit including a plurality of fuse elements situated in a matrix formation, the identification circuit being connected to the fuse means of the enable latch, wherein

at least one of the plurality of fuse elements is fused when the fuse means of the enable latch is fused thereby providing identification information in the identification circuit regarding the semiconductor device.

16. The semiconductor device according to claim 15, wherein at least one of the plurality of fuse elements is fused in accordance with information for a wafer.

17. The semiconductor device according to claim 15, wherein at least one of the plurality of fuse elements is fused in accordance with position information within a wafer.

18. A semiconductor device including a semiconductor substrate having a plurality of circuit elements, the semiconductor device further comprising:

an identification circuit including registration means for recording identification information and read means for reading the identification information from the registration means, wherein

the registration means comprises a plurality of fuse elements connected to I/O pads.

19. The semiconductor device according to claim 18, wherein the read means comprises a plurality of FETs having respective drains connected to a power supply V_DD.

20. The semiconductor device according to claim 19, wherein each of the plurality of fuse elements is connected in series with a respective source of the plurality of FETs.

21. The semiconductor device according to claim 18, wherein at least one of the plurality of fuse elements is fused to provide the identification information.