High voltage transistor having reduced on-resistance

• US 5,294,824 A
• Filed: 07/31/1992
• Issued: 03/15/1994
• Est. Priority Date: 07/31/1992
• Status: Expired due to Term

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Okada, David N.
• Primary Examiner(s): Hille, Rolf
• Assistant Examiner(s): LOKE, STEVEN HO YIN
• Application Number:
  US07/922,718
• Time in Patent Office: 592 Days
• Field of Search: 257/339, 257/342, 257/343, 257/409, 257/327
• US Class Current: 257/409
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

A method for forming a plurality of surface conduction paths (33) in a conductive region (16) of a first conductivity type. A plurality of areas (17) of a second conductivity type are formed in the conductive region (16). The plurality of areas (17) deplete the conductive region (16) when a reverse bias voltage is placed across the conductive region (16) and the plurality of areas (17). Area of the conductive region (16) adjacent to each of the plurality of areas (17) form the plurality of surface conduction paths (33) for conducting current through the conductive region (16).

Claims

1. A high voltage transistor comprising:

a semiconductor substrate of a first conductivity type;

a source of a second conductivity type formed in the semiconductor substrate;

an extended drain region of said second conductivity type formed in the semiconductor substrate a predetermined distance from said source;

a drain of said second conductivity type formed in said extended darin region;

a plurality of areas of said first conductivity type formed in said extended drain region in a predetermined manner with respect to each other, said plurality of areas being contained in said extended drain region and separate from one another;

an insulation layer formed on said semiconductor substrate between said source and said extended drain region wherein sad insulation layer overlaps said source and said extended drain region; and

a layer of conductive material formed on said insulation layer forming a gate.

2. The high voltage transistor of claim 1 further including:

an area formed of said first conductivity type in said semiconductor substrate between said source and said extended drain region wherein said area formed of said first conductivity type is coupled to the source;

said insulation layer being silicon dioxide; and

said layer of conductive material being doped polysilicon.

3. The high voltage transistor of claim 1 wherein said plurality of areas of said first conductivity type formed in said extended drain region being parallel rectangular areas.

4. The high voltage transistor of claim 3 wherein said parallel rectangular areas are formed between said drain and said source.

5. A high voltage transistor comprising:

a semiconductor substrate of a first conductivity type;

a source of a second conductivity type formed in the semiconductor substrate;

an extended drain region of said second conductivity type formed in the semiconductor substrate a predetermined distance from said source;

a drain of said second conductivity type formed in said extended drain region;

a plurality of areas of said first conductivity type formed in said extended drain region in a predetermined manner with respect to each other, said plurality of areas being contained in said extended drain region and said plurality of areas being parallel rectangular areas formed between said drain and said source wherein said parallel rectangular areas and said semiconductor substrate fully deplete said extended drain region at a voltage substantially equal to a breakdown voltage of said high voltage transistor wherein said parallel rectangular areas are at a similar voltage as said source of said high voltage transistor;

an insulation layer formed on said semiconductor substrate between said source and said extended drain region wherein said insulation layer overlaps said source and said extended drain region; and

a layer of conductive material formed on said insulation layer forming a gate.

6. The high voltage transistor of claim 5 wherein each of said parallel rectangular areas has a first side facing said source and wherein each of said parallel rectangular areas has a second side facing said drain.

7. The high voltage transistor of claim 6 wherein a plurality of surface conduction paths conduct current in said extended drain region when said high voltage transistor is in an on-state.

8. The high voltage transistor of claim 7 wherein said plurality of surface conduction paths comprises area of said extended drain region adjacent to each of said parallel rectangular areas.

9. A transistor comprising:

a first conductive region of a first conductivity type;

a second conductive region of a second conductivity type formed in said first conductive region, said second conductive region provides a conductive path when the transistor is enabled; and

a plurality of areas of said first conductivity type formed in said second conductive region, said plurality of areas are spaced a predetermined distance from one another and area of said second conductive region between said plurality of areas form a plurality of surface conduction paths for conducting current when the transistor is enabled, said plurality of areas are separate from one another and contained within said second conductive region.

10. The transistor of claim 9 further including:

a third conductive region of said second conductivity type formed in said second conductive region, said third conductive region forms a drain region for the transistor;

a fourth conductive region of said second conductivity type formed in said first conductive region a predetermined distance from said second conductive region, said fourth conductive region forming a source region of the transistor; and

a gate for coupling said fourth conductive region to said second conductive region when a voltage bias is applied to said gate.

11. The transistor of claim 10 wherein said plurality of areas are placed between said third conductive region and said fourth conductive region.

12. The transistor of claim 11 wherein said plurality of areas are formed as a plurality of parallel rectangular areas, said plurality of parallel rectangular areas are aligned such that said plurality of conduction paths couple said source region to said drain region when the transistor is enabled.

13. A transistor comprising:

a first conductive region of a first conductivity type;

a second conductive region of a second conductivity type formed in said first conductive region, said second conductive region providing a conductive path when the transistor is enabled;

a plurality of areas of said first conductivity type formed in said second conductive region, said plurality of areas are spaced a predetermined distance from one another and area of said second conductive region between said plurality of areas form a plurality of surface conduction paths for conducting current when the transistor is enabled, said plurality of areas being contained within said second conductive region and being formed as a plurality of parallel rectangular areas having two short sides and two long sides;

a third conductive region of said second conductivity type formed in said second conductive region, said third conductive region forms a drain region for the transistor;

a fourth conductive region of said second conductivity type formed in said fist conductive region a predetermined distance from said second conductive region, said fourth conductive region forming a source region of the transistor wherein said plurality of parallel rectangular areas are placed between said third conductive region and said fourth conductive region, wherein said plurality of parallel rectangular areas are aligned such that a short side of each rectangular area faces either said third or fourth conductive region, wherein area of said second conductive region between said parallel rectangular areas form said plurality of conductive paths to said third conductive region and wherein said plurality of parallel rectangular areas are spaced a predetermined distance from one another and are surrounded by the second conductive region, said predetermined distance is chosen to deplete area between said parallel rectangular areas at a predetermined reverse bias voltage between said second conductive region and said plurality of parallel rectangular areas; and

a gate for coupling said fourth conductive region to said second conductive region when a voltage bias is applied to said gate.

14. The transistor of claim 13 wherein said plurality of parallel rectangular areas is coupled to a voltage potential through a depletion region formed by said second conductive region and said first conductive region.

15. The transistor of claim 14 wherein said second conductive region being fully depleted by said plurality of parallel rectangular areas and said first conductive region to maximize breakdown voltage of the transistor.