Arrangement for monitoring the bit rate in ATM networks
First Claim
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1. A system for bit rate monitoring in an ATM network, comprising:
- first leaky bucket means for monitoring a constant bit rate rc or a peak bit rate rp =Bz ·
d1 /T1, where Bz =plurality of bits per ATM cell, d1 =deincrementation value ant T1 =deincrementation period of the first leaky bucket means, and defining for a fullrate burst a maximum possible plurality nmax =s1 +kd1 of ATM cells up to a response of the first leaky bucket means, where k=1+ (s1 -d1)/((T1 /tz)-d1)⊥
, s1 =response threshold of the first leaky bucket means, and tz =duration of an ATM cell at a maximum transmission rate;
second leaky bucket means for monitoring an average bit rate ra =Bz ·
d2 /T2, where d2 =deincrementation value and T2 =deincrementation period of the second leaky bucket means, and defining a maximum duration tmax ≈
s2 ·
Bz /(rp -ra) of a peak rate burst where s2 =response threshold of the second leaky bucket means;
said second leaky bucket means having first, second, and third counter means;
said first counter means having said response threshold s2 and also a reset threshold sR for resetting the first counter means to zero upon a downward transgression thereof, said reset threshold sR lying just before said response threshold S2, said response threshold s2 having a counter reading which is incremented with ATM cells arriving in said second leaky bucket means, and being deincremented by said deincrementation value d2 with said deincrementation period T2 ;
said third counter means also being connected to be incremented with said ATM cells fed to said second leaky bucket means and being deincremented by means for providing a respective counting step with a cell clock rate RR dependent on a degree of filling of said third counter means;
said second counter means also being connected to be deincremented by said deincrementation value d2 with said deincrementation period T2, and also being connected for being simultaneously incremented with said deincrementation of said third counter means; and
said second counter means having a response threshold s2 * which is lower than the response threshold s2 of said first counter means, either of said s2 * or s2 response thresholds when reached resulting in an elimination or marking of excess ATM cells.
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Abstract
For dual leaky bucket ATM bit rate monitoring, a peak bit rate is monitored in a first leaky bucket unit and a maximum cell plurality of a full rate burst is defined. A duration of peak rate bursts is monitored in a second leaky bucket unit with a first counter respectively reset to 0 when the counter reading returns below a defined value. An average bit rate is monitored with a further counter having a lower response value that is incremented with a cell rate which is smoothed dependent on a degree of filling in an additional cell counter.
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Citations
12 Claims
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1. A system for bit rate monitoring in an ATM network, comprising:
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first leaky bucket means for monitoring a constant bit rate rc or a peak bit rate rp =Bz ·
d1 /T1, where Bz =plurality of bits per ATM cell, d1 =deincrementation value ant T1 =deincrementation period of the first leaky bucket means, and defining for a fullrate burst a maximum possible plurality nmax =s1 +kd1 of ATM cells up to a response of the first leaky bucket means, where k=1+ (s1 -d1)/((T1 /tz)-d1)⊥
, s1 =response threshold of the first leaky bucket means, and tz =duration of an ATM cell at a maximum transmission rate;second leaky bucket means for monitoring an average bit rate ra =Bz ·
d2 /T2, where d2 =deincrementation value and T2 =deincrementation period of the second leaky bucket means, and defining a maximum duration tmax ≈
s2 ·
Bz /(rp -ra) of a peak rate burst where s2 =response threshold of the second leaky bucket means;said second leaky bucket means having first, second, and third counter means; said first counter means having said response threshold s2 and also a reset threshold sR for resetting the first counter means to zero upon a downward transgression thereof, said reset threshold sR lying just before said response threshold S2, said response threshold s2 having a counter reading which is incremented with ATM cells arriving in said second leaky bucket means, and being deincremented by said deincrementation value d2 with said deincrementation period T2 ; said third counter means also being connected to be incremented with said ATM cells fed to said second leaky bucket means and being deincremented by means for providing a respective counting step with a cell clock rate RR dependent on a degree of filling of said third counter means; said second counter means also being connected to be deincremented by said deincrementation value d2 with said deincrementation period T2, and also being connected for being simultaneously incremented with said deincrementation of said third counter means; and said second counter means having a response threshold s2 * which is lower than the response threshold s2 of said first counter means, either of said s2 * or s2 response thresholds when reached resulting in an elimination or marking of excess ATM cells. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A system for bit rate monitoring in an ATM network and for eliminating excess ATM cells, comprising:
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a cell line; a first elimination means connected to said cell line which, when activated, eliminates undesired ATM cells; a second elimination means in said cell line which, when activated, also eliminates undesired ATM cells from said cell line; a first leaky bucket unit means connected to said first elimination means for monitoring a peak bit rate and for defining a maximum cell number of a full rate burst; a second leaky bucket means connected to said second elimination means for monitoring a duration of peak rate bursts; and said second leaky bucket means having a first counter and means for resetting said first counter to zero when a counter reading thereof downward transgresses a defined response threshold, a second counter means for monitoring an average bit rate and having a response value which is lower than said response value of said first counter, and said second counter means being incremented with a cell rate which is smoothed dependent on a degree of filling in a third cell counter contained in said leaky bucket unit means.
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11. A system for bit rate monitoring and for eliminating excess ATM cells in ATM networks, comprising:
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a cell line over with said ATM cells pass and having first and second elimination switches connected in series; a first leaky bucket unit containing a counter having an input connected to receive said ATM cells from said cell line, having a further input at which a deincrementation value and a deincrementation period are input, and having a response threshold output connected to trigger said first elimination switch in said cell line; and a second leaky bucket unit having said second elimination switch, first, second, and third counters, said first counter connected to receive ATM cells from said cell line at a first input, a second input at which deincrementation signals for a deincrementation by a deincrementation value with a deincrementation period are input, a third input receiving feedback from a first response threshold at a first output, and a second output as a second response threshold connected through a logic element to drive said second elimination switch, said third counter having a first input connected to receive ATM cells from said cell line, a plurality of outputs connected to a cell clock generator means for determining a filling state of said third counter, and an output of the cell clock generator means connected as a feedback input back to a second input of said third counter and also connected through said second counter and through said logic element to said second elimination switch. - View Dependent Claims (12)
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Specification