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Arrangement for monitoring the bit rate in ATM networks

  • US 5,295,135 A
  • Filed: 08/20/1992
  • Issued: 03/15/1994
  • Est. Priority Date: 08/27/1991
  • Status: Expired due to Fees
First Claim
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1. A system for bit rate monitoring in an ATM network, comprising:

  • first leaky bucket means for monitoring a constant bit rate rc or a peak bit rate rp =Bz ·

    d1 /T1, where Bz =plurality of bits per ATM cell, d1 =deincrementation value ant T1 =deincrementation period of the first leaky bucket means, and defining for a fullrate burst a maximum possible plurality nmax =s1 +kd1 of ATM cells up to a response of the first leaky bucket means, where k=1+ (s1 -d1)/((T1 /tz)-d1)⊥

    , s1 =response threshold of the first leaky bucket means, and tz =duration of an ATM cell at a maximum transmission rate;

    second leaky bucket means for monitoring an average bit rate ra =Bz ·

    d2 /T2, where d2 =deincrementation value and T2 =deincrementation period of the second leaky bucket means, and defining a maximum duration tmax

    s2 ·

    Bz /(rp -ra) of a peak rate burst where s2 =response threshold of the second leaky bucket means;

    said second leaky bucket means having first, second, and third counter means;

    said first counter means having said response threshold s2 and also a reset threshold sR for resetting the first counter means to zero upon a downward transgression thereof, said reset threshold sR lying just before said response threshold S2, said response threshold s2 having a counter reading which is incremented with ATM cells arriving in said second leaky bucket means, and being deincremented by said deincrementation value d2 with said deincrementation period T2 ;

    said third counter means also being connected to be incremented with said ATM cells fed to said second leaky bucket means and being deincremented by means for providing a respective counting step with a cell clock rate RR dependent on a degree of filling of said third counter means;

    said second counter means also being connected to be deincremented by said deincrementation value d2 with said deincrementation period T2, and also being connected for being simultaneously incremented with said deincrementation of said third counter means; and

    said second counter means having a response threshold s2 * which is lower than the response threshold s2 of said first counter means, either of said s2 * or s2 response thresholds when reached resulting in an elimination or marking of excess ATM cells.

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