Equalization method utilizing a delay circuit

• US 5,295,157 A
• Filed: 05/27/1992
• Issued: 03/15/1994
• Est. Priority Date: 06/04/1991
• Status: Expired due to Fees

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Suzuki, Mitsuhiro, Kunihiro, Takushi
• Primary Examiner(s): Chin, Stephen
• Assistant Examiner(s): Webster, Bryan E.
• Application Number:
  US07/888,498
• Time in Patent Office: 657 Days
• Field of Search: 375/11, 375/12, 375/14, 364/724.19, 364/724.2
• US Class Current: 375/229
• CPC Class Codes: H04L 25/03038 with a non-recursive structure H04L25/03031 takes precedence

Abstract

An input signal composed of a predetermined total number of symbols is supplied to a series circuit of delay units. The input signal and delayed output signals from the delay units are multiplied by coefficients, and the products are added into an equalized output signal. The supplied input signal is transmitted, successively in normal, opposite, and normal directions, through a predetermined number of delay units corresponding to a unit number of symbols which is smaller than the predetermined total number of symbols to delay the input signal successively with those delay units. Each time the input signal is transmitted in the series circuit in one of the directions, an amplitude error of the equalized output signal is detected. In order to minimize the amplitude error, coefficients by which to multiply the input signal and the delayed output signals are calculated depending on the detected amplitude error. Alternatively, the input signal is divided into a plurality of blocks each composed of a predetermined number of symbols, and supplied to the series circuit to produce an equalized output signal of each of the blocks. An error signal is calculated which is composed of the sum of squares of differences between the equalized output signals and a reference signal. The coefficients are calculated depending on the rates of change of the error signal relative to the coefficients.

Claims

1. An equalization method for supplying an input signal composed of a predetermined total number of symbols to a series circuit of plural delay means, multiplying the input signal and delayed output signals from the delay means by coefficients, and adding the products into an equalized output signal, said equalization method comprising the steps of:

supplying the input signal to the series circuit;

transmitting the input signal in a first direction through a predetermined number of delay means corresponding to a unit number of symbols which is smaller than said predetermined total number of symbols to delay the input signal successively with the delay means;

transmitting again the input signal in a second direction opposite to the first direction through said predetermined number of delay means to delay the input signal successively with the delay means;

transmitting again the input signal in the first direction through said predetermined number of delay means to delay the input signal successively with the delay means;

detecting an amplitude error of the equalized output signal each time the input signal is transmitted in the series circuit in the first direction or second direction; and

calculating said coefficients multiplied with the input signal and the delayed output signals from the respective delay means according to the detected amplitude error whereby the amplitude error is minimized.

2. The method of claim 1 wherein the input signal is received from a cellular telecommunication transmission.

3. The method of claim 1 wherein the input signals are applied to a π

/4-shifted quadrature phase keying modulator.

4. An equalization method comprising the steps of:

dividing an input signal into a plurality of blocks each composed of a predetermined number of symbols;

supplying the input signal to a series circuit which includes a predetermined number of delay means corresponding to a unit number of symbols which is smaller than said predetermined total number of symbols;

transmitting the input signal in a first direction through the delay means to delay the input signal sequentially with the delay means;

transmitting again the input signal in a second direction opposite to the first direction through said predetermined number of delay means to delay the input signal successively with the delay means;

transmitting again the input signal in the first direction through said predetermined number of delay means to delay the input signal successively with the delay means;

detecting an amplitude error of the equalized output signal each time the input signal is transmitted in the series circuit in the first direction or second direction

calculating an error signal associated with each of said blocks which is composed of the sum of squares of differences between the equalized output signals and a reference signal;

determining the rate of change of each error signal associated with each of said blocks; and

varying the coefficients by which to multiply the delayed output signals from the delay means according to each of said rate of change of each error signal with respect to the coefficients.

5. The method of claim 4 wherein the input signal is received from a cellular telecommunication transmission.

6. The method of claim 4 wherein the input signals are applied to a π

/4-shifted quadrature phase keying modulator.