Fiber optic amplifier with active elements feedback circuit

• US 5,295,161 A
• Filed: 05/10/1991
• Issued: 03/15/1994
• Est. Priority Date: 05/10/1991
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Dreps, Daniel M., Rizzo, Raymond P.
• Primary Examiner(s): Kuntz, Curtis
• Assistant Examiner(s): GHEBRETINSAE, TEMESGHEN
• Application Number:
  US07/698,626
• Time in Patent Office: 1,040 Days
• Field of Search: 375/17, 375/19, 375/36, 375/76, 330/261, 330/265, 330/270, 330/311, 330/9, 330/259, 330/252, 330/59, 330/308, 330/260, 307/359, 307/491, 307/495
• US Class Current: 375/318
• CPC Class Codes: H03F 3/08 controlled by light
• CPC Class Codes: H04B 10/6933 Offset control of the differential preamplifier

Abstract

A differential transimpedance amplifier used in amplifying optical signals transmitted with a balanced code has a level restore circuit which integrates the digital output of the amplifier and feeds back the result to one of the differential inputs of the amplifier. The feedback signal removes imbalances from the amplifier output. The balanced amplifier output can then be processed by a clock reconstruction circuit to accurately sample the received optical signal with a low bit error rate.

Claims

1. A receiver for recovering multibit binary digital messages from transmitted balanced code, comprising:

a differential amplifier for amplifying received balanced code and supplying high and low digital output signals; and

an active elements level restore circuit coupled to the digital output of the amplifier, said active elements level restore circuit comprising means for determining a pulse width difference between the high and low digital signals provided by said amplifier and means for integrating the pulse width difference and supplying said integrated pulse width difference to one of said inputs of said differential amplifier, so that a balanced digital output from said amplifier is achieved.

2. The receiver of claim 1, wherein said means for determining the pulse width difference comprises a current source, a switchable current sink in series with said current source, said switchable current sink sinking twice the current provided by said current source, said switchable current sink responsive to the digital output of said amplifier, with said switchable current sink sinking current from said current source only when said digital output is at one of its two logic levels, a signal proportional to the pulse width difference provided at the junction of said current source and switchable current sink.

3. The receiver of claim 2 wherein said means for integrating comprises a capacitor coupled to the junction of said current source and said switchable current sink.

4. The receiver of claim 3 wherein said amplifier has a band-pass characteristic selected to pass the longest high and longest low level run length expected from said balanced code, and said capacitor value selected to reduce the amplifier gain at frequencies below the band-pass frequencies.

5. The receiver of claim 3 wherein said level restore circuit further comprises trim means for balancing said current source and current sink means.

6. The receiver of claim 5 wherein said trim means comprises a variable resistor coupled to a voltage source for supplying or removing current from the junction of said current source and said switchable current sink.

7. The receiver of claim 4 wherein said differential amplifier comprises a differential transimpedance amplifier.

8. A fiber optic receiver for recovering multibit binary digital messages from optically transmitted balanced code comprising:

a photo-detector circuit for converting the received optical signals into electrical signals;

a differential amplifier AC coupled to the photo-detector circuit for amplifying the electrical signals and supplying high and low digital output signals; and

an active elements level restore circuit coupled to the digital output of the amplifier, said active elements level restore circuit comprising means for determining a pulse width difference between the high and low digital signals provided by said amplifier and means for integrating the pulse width difference and supplying said integrated pulse width difference to one of said inputs of said differential amplifier, so that a balanced digital output from said amplifier is achieved.

9. The receiver of claim 8, wherein said means for determining the pulse width difference comprises a current source, a switchable current sink in series with said current source, said switchable current sink sinking twice the current provided by said current source, said switchable current sink responsive to the digital output of said amplifier, with said switchable current sink sinking current from said current source only when said digital output is at a one of its two logic levels, a signal proportional to the pulse width difference provided at the junction of said current source and switchable current sink.

10. The receiver of claim 9 wherein said means for integrating comprises a capacitor coupled to the junction of said current source and said switchable current sink.

11. The receiver of claim 10 wherein said amplifier has a band-pass characteristic selected to pass the longest high and longest low level run length expected from said balanced code, and said capacitor value selected to reduce the amplifier gain at frequencies below the band-pass frequencies.

12. The receiver of claim 10 wherein said level restore circuit further comprises trim means for balancing said current source and current sink means.

13. The receiver of claim 12 wherein said trim means comprises a variable resistor coupled to a power source for supplying or removing current from the junction of said current source and said switchable current sink.

14. The receiver of claim 10 wherein said differential amplifier comprises a differential transimpedance amplifier.