Method of forming trench isolated regions with sidewall doping

• US 5,296,392 A
• Filed: 02/24/1992
• Issued: 03/22/1994
• Est. Priority Date: 03/06/1990
• Status: Expired due to Term

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Digital Equipment Corporation (HP Inc.)
• Inventors: Metz, Walter C., Grula, Gregory J.
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): OJAN, OURMAZD
• Application Number:
  US07/841,239
• Time in Patent Office: 757 Days
• Field of Search: 437/67, 437/57, 437/160, 437/162, 437/228, 437/34, 437/56
• US Class Current: 438/222
• CPC Class Codes: H01L 21/2257 the applied layer being silicon or silicide or SIPOS, e.g. polysilicon, porous silicon
• CPC Class Codes: H01L 21/76237 introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure

Abstract

In a semiconductor substrate, a method of forming a shallow isolation trench having a doped sidewall is disclosed. A shallow trench having nearly vertical walls is formed in the semiconductor substrate. A doped silicon layer is selectively grown on a sidewall and a portion of the bottom of the trench. The dopant from the silicon layer is then driven into the substrate by a suitable method such as annealing. The trench is subsequently filled with a dielectric material.

Claims

1. A method of making a semiconductor device having an isolation trench in a face of a silicon wafer, said wafer having an N-type area in said face adjacent a P-type area on said face, said N-type area being formed in said face using a first mask, said method comprising the steps of:

(a) after said N-well has been formed, forming a trench in a first area of said face of the silicon wafer using a second mask, said first area being different in shape on said face than said N-type area, said trench being at and on both sides of an interface between said N-type and P-type areas of said face of the wafer, said trench having nearly vertical side walls and having a bottom surface extending across said interface so that an N-type trench area and a P-type trench area are exposed in the bottom surface of the trench on both sides of said interface;

(b) selectively forming a silicon layer on one said wall and on a portion of the bottom surface of the trench over said P-type trench area and extending across said interface but not covering the major part of said N-type trench area of the bottom of the trench, said silicon layer being patterned using a third mask different from said first and second masks to define a second area of a shape on said face different from said N-type area and said first area so that said silicon layer extends across said interface, said silicon layer having a conductivity type dopant concentration which is greater than a P-type dopant concentration of said P-type area of the silicon wafer;

(c) heating the wafer at a temperature and for a time which are sufficient to drive a part of the dopant from the silicon layer into the silicon wafer; and

(d) filling the trench with a dielectric material.

2. The method of claim 1 wherein said trench is about 5000 Angstroms deep and between 5000-1000 Angstroms wide.

3. The method of claim 2 wherein said silicon layer is an epitaxial layer between 400-500 Angstroms thick.

4. The method of claim 1 wherein said silicon layer is a polysilicon layer between 400-500 Angstroms thick.

5. A method of forming an isolation trench in a face of a P-type substrate having an N-well at said face, the area of said N-well on said face being of a first shape, said method comprising the steps of:

(a) using a mask of an area of said face of a second shape different from said first shape, with edges of said second shape being laterally spaced on said face from edges of said first shape, forming a trench in said face of the P-type substrate extending across an interface between said N-well and said P-type substrate, said trench having near vertical walls and a near horizontal bottom separating the walls;

said bottom of said trench extending across said interface;

(b) selectively forming a P-type silicon layer in an area of said face of a third shape different from said first and second shapes and only on selected P-type portions of the trench walls and bottom and extending across said interface;

with edges of said third shape being laterally spaced on said face from edges of said second shape on said face;

(c) forming a thin oxide layer on the silicon layer; and

(d) depositing a silicon dioxide coating on said face of the silicon substrate thereby completely filling the isolation trench;

(e) depositing a photoresist layer on said face of the silicon substrate to obtain a near planar surface; and

(f) etching back both the photoresist and the silicon dioxide layer at said face until the silicon substrate is exposed to provide a planar surface.

6. A method of fabricating a CMOS device on a face of a first conductivity type silicon substrate having a second conductivity type well and an interface between said well and said substrate, said well being in an are of said face which is of a first shape on said face, said method comprising the steps of:

(a) forming a trench in said face in an area of said face which is of a second shape different from said first shape, said trench having near vertical walls and a bottom surface separating said walls, said trench also separating a first active region in the substrate from a second active region in the well and a bottom area of said trench extending across said interface between the well and the substrate;

edges of said second shape being laterally spaced on said face from edges of said first shape;

(b) selectively forming a first conductivity type silicon layer in the trench while masking the walls of the trench in said well, said silicon layer also rounding trench corners, said silicon layer further having first conductivity type concentration which is greater than the concentration of the silicon substrate, said silicon layer being formed in an area of said face having a third shape on said face different from said first ad second shapes;

edges of said third shape being laterally spaced on said face from edges of said second shape;

(c) heating the substrate at a temperature and for a time which is sufficient to drive the first conductivity type impurity from the silicon layer into the substrate;

(d) filling the trench with a dielectric material; and

(e) forming a first-conductivity-type-channel transistor in the second active region and a second-conductivity-type-channel transistor in the first active region.

8. The method as described in claim 6 wherein said trench is between 5000-10000 Angstroms wide and about 5000 Angstroms deep, and said silicon layer is less than 500 Angstroms thick.

7. A method of forming an isolation trench in a face of a silicon substrate having a predetermined amount of P-type dopant concentration and having an N-well in said substrate, with an interface at said face between said well and the substrate, said N-well formed using a first mask so that the N-well occupies a first area of said face of said substrate, said method comprising the steps of:

(a) forming a trench in said face of the silicon substrate using a second mask different from said first mask so that said trench occupies a second area of said face different from said first area, said trench having near vertical walls and a nearly flat bottom area separating the trench walls, said bottom area extending across said interface between the P-type substrate and the N-well;

(b) using a third mask different from said first and second masks, selectively forming an oxide layer on selected portions of the walls and the bottom area of the trench on said N-well and leaving bare the walls and bottom area of said trench on P-type said substrate;

(c) exposing the silicon substrate to anhydrous hydrogen chloride (HCL) gas and thereafter adding to the HCL a mixture of dichlorosilane and diborane in hydrogen at a predetermined temperature and for a predetermined time to controllably grow a silicon layer of a predetermined thickness, said diborane doping the silicon layer with a P-type impurity concentration that is greater than the P-type dopant concentration of the silicon substrate;

(d) driving some of the P-type dopant concentration from the silicon layer to the P-type silicon substrate; and

(e) filling the trench with an oxide to obtain a planar silicon substrate surface having the isolation trench.

9. The method as described in claim 7 wherein said temperature and said time in step (c) are about 950 degrees Celsius and about 30 seconds respectively.