Method of making n-channel and p-channel junction field-effect transistors and CMOS transistors using a CMOS or bipolar/CMOS process
First Claim
1. A method of fabricating elements of a junction field-effect transistor while simultaneously fabricating the elements of a first metal-oxide-semiconductor transistor and a second metal-oxide-semiconductor transistor having a channel conductivity of the opposite type to the first metal-oxide-semiconductor transistor, the transistors each having a source, a drain, a gate, and a channel region, the method comprising the steps of:
- (a) providing a substrate (2) of a semiconductor material having a conductivity of a first type and including,(i) a first part, a portion of the first part forming the channel region of the second metal-oxide-semiconductor transistor (3), and(ii) a second part, including a MOS channel well region (13) of a second conductivity type, opposite to the first conductivity type, the MOS channel well region forming the channel region of the first metal-oxide-semiconductor transistor (1);
(b) introducing an impurity into first selected regions (31,
33) in the first part of the substrate to form the source and drain of the second metal-oxide-semiconductor transistor, and into a second selected region (35) and a third selected region (37) in the first part of the substrate to form the source and drain, respectively, of the junction field-effect transistor (5), such that the first selected regions, the second selected region, and the third selected region are of the second conductivity type;
(c) introducing an impurity into a fourth selected region (19), substantially bounded by the third selected region, to form the channel region of the junction field-effect transistor, such that the fourth selected region is of the second conductivity type; and
(d) introducing an impurity into fifth selected regions (39,
41) in the MOS channel well region to form the source and drain of the first metal-oxide-semiconductor transistor, and into a sixth selected region (43) between the second selected region and the third selected region to form the gate of the junction field-effect transistor, such that the fifth selected regions and the sixth selected region are of the first conductivity type.
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Abstract
A method of making N-channel and P-channel junction field-effect transistors using a modified CMOS process that simultaneously makes complementary metal-oxide-semiconductor transistors, or a modified BiCMOS process that simultaneously makes bipolar transistors and complementary metal-oxide-semiconductor transistors. Making junction field effect transistors using the basic CMOS process requires mask changes and an additional mask, etch, and implant step. Making junction field effect transistors using the BiCMOS process only requires mask changes.
32 Citations
34 Claims
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1. A method of fabricating elements of a junction field-effect transistor while simultaneously fabricating the elements of a first metal-oxide-semiconductor transistor and a second metal-oxide-semiconductor transistor having a channel conductivity of the opposite type to the first metal-oxide-semiconductor transistor, the transistors each having a source, a drain, a gate, and a channel region, the method comprising the steps of:
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(a) providing a substrate (2) of a semiconductor material having a conductivity of a first type and including, (i) a first part, a portion of the first part forming the channel region of the second metal-oxide-semiconductor transistor (3), and (ii) a second part, including a MOS channel well region (13) of a second conductivity type, opposite to the first conductivity type, the MOS channel well region forming the channel region of the first metal-oxide-semiconductor transistor (1); (b) introducing an impurity into first selected regions (31,
33) in the first part of the substrate to form the source and drain of the second metal-oxide-semiconductor transistor, and into a second selected region (35) and a third selected region (37) in the first part of the substrate to form the source and drain, respectively, of the junction field-effect transistor (5), such that the first selected regions, the second selected region, and the third selected region are of the second conductivity type;(c) introducing an impurity into a fourth selected region (19), substantially bounded by the third selected region, to form the channel region of the junction field-effect transistor, such that the fourth selected region is of the second conductivity type; and (d) introducing an impurity into fifth selected regions (39,
41) in the MOS channel well region to form the source and drain of the first metal-oxide-semiconductor transistor, and into a sixth selected region (43) between the second selected region and the third selected region to form the gate of the junction field-effect transistor, such that the fifth selected regions and the sixth selected region are of the first conductivity type. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A method of fabricating elements of a junction field-effect transistor while simultaneously fabricating the elements of a first metal-oxide-semiconductor transistor and a second metal-oxide-semiconductor transistor having a channel conductivity of the opposite second type to the first metal-oxide-semiconductor transistor, the metal-oxide-semiconductor transistors each having a source, a drain, a gate, and a channel region, and the junction field-effect transistor additionally having a back gate, the method including the steps of:
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(a) providing a substrate (2) of a semiconductor material having a conductivity of a first type, and including (i) a first part, a portion of the first part forming the channel region of the second metal-oxide-semiconductor transistor (3), and (ii) a second part, (b) introducing an impurity into an MOS channel well region (13) in the second part of the substrate to form the channel region of the first metal-oxide-semiconductor transistor (1), and into a JFET well region (47) in the second part of the substrate to form the back gate of the junction field-effect transistor (7), such that the MOS channel well region and the JFET well region are of a second conductivity type, opposite to the first conductivity type; (c) introducing an impurity into first selected regions (31,
33) in the first part of the substrate to form the source and drain of the second metal-oxide-semiconductor transistor, and into a second selected region (51) in the JFET well region to form the gate of the junction field-effect transistor, such that the first selected regions and the second selected region are of the second conductivity type;(d) introducing an impurity into a third selected region (50) in the JFET well region to form the channel region of the junction field-effect transistor, such that the third selected region is of the first conductivity type; (e) introducing an impurity into fourth selected regions (39,
41) in the MOS channel well region to form the source and drain of the first metal-oxide-semiconductor transistor, and into a fifth selected region (55) and a sixth selected region (57) in the third selected region, adjacent to the second selected region, to form the source and drain, respectively, of the junction field-effect transistor, such that the fourth selected regions, the fifth selected region, and the sixth selected region are of the first conductivity type. - View Dependent Claims (8, 9, 10, 11, 12, 13, 14, 15, 16)
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17. A method of fabricating elements of a junction field-effect transistor having a source, a drain, a gate, and a channel region, while simultaneously fabricating the elements of a first metal-oxide-semiconductor transistor, a second metal-oxide-semiconductor transistor having a channel conductivity of the opposite type to the first metal-oxide-semiconductor transistor, the metal-oxide-semiconductor transistors each having a source, a drain, a gate, and a channel region, and a bipolar transistor having a collector, a base, and an emitter, the method comprising the steps of:
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(a) providing a substrate (67) of a semiconductor material having a conductivity of a first type and including; (i) a surface (69), (ii) a buried layer (73) of the first conductivity type formed therein below the surface, and (iii) a buried layer (71) of a second conductivity type, opposite to the first conductivity type, formed therein below the surface; (b) introducing an impurity into a collector well region (79) of the substrate above the buried layer of the second conductivity type to form the collector of the bipolar transistor (65), into a first MOS channel well region (81) of the substrate to form the channel region of the first metal-oxide-semiconductor transistor (61), and into a JFET well region (113) of the substrate above the buried layer of the first conductivity type to form the channel region of the junction field-effect transistor (111), such that the collector well region, the first MOS channel well region, and the JFET well region are of the second conductivity type; (c) introducing an impurity into a second MOS channel well region (85) of the substrate to form the channel region of the second metal-oxide-semiconductor transistor (63), and into a first selected region (86) within the collector well region to form the base of the bipolar transistor, such that the second MOS channel well region and the first selected region are of the first conductivity type; (d) introducing an impurity into a second selected region (117) and into a third selected region (119) in the JFET well region to form the source and drain, respectively, of the junction field-effect transistor, into fourth selected regions (97,
99) in the second MOS channel well region to form the source and drain of the second metal-oxide-semiconductor transistor, and into a fifth selected region (101) within the first selected region to form the emitter of the bipolar transistor, such that the second selected region, the third selected region, the fourth selected regions, and the fifth selected region are of the second conductivity type; and(e) introducing an impurity into sixth selected regions (105,
107) in the first MOS channel well region to form the source and drain of the first metal-oxide-semiconductor transistor, and into a seventh selected region (121) between the second selected region and the third selected region to form the gate of the junction field-effect transistor, such that the sixth selected regions and the seventh selected region are of the first conductivity type. - View Dependent Claims (18, 19, 20, 21, 22, 23, 24)
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25. A method of fabricating elements of a junction field-effect transistor having a source, a drain, a top gate, a back gate, and a channel region, while simultaneously fabricating the elements of a first metal-oxide-semiconductor transistor, a second metal-oxide-semiconductor transistor having a channel conductivity of the opposite type to the first metal-oxide-semiconductor transistor, the metal-oxide-semiconductor transistors each having a source, a drain, a gate, and a channel region, and a bipolar transistor having a collector, a base, and an emitter, the method comprising the steps of:
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(a) providing a substrate (67) of a semiconductor material having a conductivity of a first type and including; (i) a surface (69), (ii) a first buried layer (71) of a second conductivity type, opposite to the first conductivity type, formed therein below the surface, (iii) a second buried layer of the second conductivity type (129), formed therein below the surface, at least part of the second buried layer forming the back gate of the junction field-effect transistor (127), (4) above the first buried layer of the second conductivity type, a collector well region (79) of the second conductivity type forming the collector of the bipolar transistor (65), and (5) a first MOS channel well region (81) of the second conductivity type forming the channel region of the first metal-oxide-semiconductor transistor (61); (b) introducing an impurity into a JFET well region (133) of the substrate above the second buried layer of the second conductivity type to form the channel region of the junction field-effect transistor, into a second MOS channel well region (85) of the substrate to form the channel region of the second metal-oxide-semiconductor transistor (63), and into a first selected region (86) within the collector well region to form the base of the junction transistor, such that the JFET well region, the second MOS channel well region, and the first selected region are of the first conductivity type; (c) introducing an impurity into a second selected region (137) in the JFET well region to form the top gate of the junction field-effect transistor, into third selected regions (97,
99) in the second MOS channel well region to form the source and drain of the second metal-oxide-semiconductor transistor, and into a fourth selected region (101) within the first selected region to form the emitter of the bipolar transistor, such that the second selected region, the third selected regions, and the fourth selected region are of the second conductivity type; and(d) introducing an impurity into fifth selected regions (105,
107) in the first MOS channel well region to form the source and drain of the first metal-oxide-semiconductor transistor, and into a sixth selected region (141) and a seventh selected region (143) adjacent to the second selected region to form the source and drain, respectively, of the junction field-effect transistor, such that the fifth selected regions, the sixth selected region, and the seventh selected region are of the first conductivity type. - View Dependent Claims (26, 27, 28, 29, 30, 31, 32, 33, 34)
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Specification