Semiconductor pressure sensor for sensing pressure applied thereto

• US 5,296,730 A
• Filed: 01/05/1993
• Issued: 03/22/1994
• Est. Priority Date: 01/16/1992
• Status: Expired due to Term

• Current Assignee: Oki Semiconductor Company Limited (ROHM Co., Ltd.)
• Original Assignee: OKI Electric Industry Company Limited
• Inventors: Takano, Osamu, Matsumi, Koji
• Primary Examiner(s): MINTEL, WILLIAM A
• Application Number:
  US08/000,680
• Time in Patent Office: 441 Days
• Field of Search: 257/417, 257/418, 257/419, 73/517 R, 73/720, 73/721, 73/726, 73/727, 437/901
• US Class Current: 257/417
• CPC Class Codes: B81C 1/00246 Monolithic integration, i.e. micromechanical structure and electronic processing unit are integrated on the same substrate
• CPC Class Codes: B81C 2203/0728 Pre-CMOS, i.e. forming the micromechanical structure before the CMOS circuit
• CPC Class Codes: G01L 9/0055 bonded on a diaphragm
• CPC Class Codes: Y10S 438/978 forming tapered edges on substrate or adjacent layers

Abstract

A semiconductor pressure sensor according to the present invention comprises a semiconductor substrate having a first surface, a second surface opposite to the first surface and a recess formed in the first surface, the recess defining an interior surface including a bottom surface; and a diffusion region extending from the adjacency of the bottom surface to the second surface. A pressure-sensitive resistance of the semiconductor pressure sensor is formed in the vicinity of the bottom surface of a diaphragm. Therefore, the pressure-sensitive resistance can be formed so as to be brought into alignment with the position of the diaphragm after the formation of the diaphragm. Accordingly, a semiconductor pressure sensor, which does not cause a displacement in position between the diaphragm and the pressure-sensitive resistance and is excellent in accuracy, can be easily fabricated. Further, since the pressure-sensitive resistance can be formed according to the shape of the diaphragm, the diaphragm can be reduced in size and fabricated in the form of a thin film.

Claims

1. A semiconductor pressure sensor comprising:

a semiconductor substrate having a first surface, a second surface opposite the first surface and a recess formed in the first surface, the recess defining an interior surface including a bottom surface;

a diffusion region formed in the semiconductor substrate extending from the bottom surface to the second surface; and

a conductive layer formed on the second surface, electrically connected to the diffusion region.

2. The semiconductor pressure sensor according to claim 1, wherein the semiconductor substrate comprises a first semiconductor substrate, an insulating layer formed on the first semiconductor substrate and a second semiconductor substrate formed on the insulating layer, the first semiconductor substrate having the first surface and a third surface opposite to the first surface, the second semiconductor substrate having the second surface and a fourth surface opposite to the second surface, the insulating layer sandwiched between the third surface and the fourth surface, a portion of the fourth surface constituting the bottom surface.

3. The semiconductor pressure sensor according to claim 1, wherein said diffusion region forms a piezoresistor element.

4. A semiconductor pressure sensor comprising:

a semiconductor substrate having a first surface, a second surface opposite to the first surface and a recess formed in the first surface, the recess defining an interior surface including a bottom surface;

an impurity layer formed in the semiconductor substrate extending from the bottom surface to the second surface, wherein the impurity layer forms a piezoresistor element; and

a conductive layer formed on the second surface, electrically connected to the diffusion region.

5. The semiconductor pressure sensor according to claim 4, wherein the semiconductor substrate comprises a first semiconductor substrate, an insulating layer formed on the first semiconductor substrate and a second semiconductor substrate formed on the insulating layer, the first semiconductor substrate having the first surface and a third surface opposite to the first surface, the second semiconductor substrate having the second surface and a fourth surface opposite the second surface, the insulating layer sandwiched between the third surface and the fourth surface, a portion of the fourth surface constituting the bottom surface.