Low pass filter circuit device and method having selectable cutoff frequency

• US 5,296,822 A
• Filed: 12/31/1992
• Issued: 03/22/1994
• Est. Priority Date: 12/31/1992
• Status: Expired due to Fees

• Current Assignee: Northrop Grumman Corporation
• Original Assignee: Westinghouse Electric Company LLC (Brookfield Asset Management Incorporated)
• Inventors: Cockey, Edward A. IV
• Primary Examiner(s): Pascal, Robert J.
• Assistant Examiner(s): DUDEK, JAMES A
• Application Number:
  US07/999,754
• Time in Patent Office: 446 Days
• Field of Search: 333/173, 333/174, 333/168, 307/520, 307/521, 330/306, 330/107, 330/302, 330/303, 330/305, 328/167
• US Class Current: 330/306
• CPC Class Codes: H03H 19/004 Switched capacitor networks

Abstract

A device and method is provided for filtering frequency components of an electrical signal above a selectable low pass cutoff frequency which is changeable within a designated range. An input filter having a fixed low pass cutoff frequency provides aliasing protection for a first of at least three clock driven filter stages respectively having variable low pass cutoff frequencies proportional to a clock rate of a received clock signal. The overall selectable low pass filter is determined at an intermediate stage of the clock driven filter stages. Clock rates of respective clock signals applied to clock driven stages proceeding the intermediate stage having the selectable cutoff frequency are adjusted so that each provides aliasing protection for the next. Similarly, the low pass cutoff frequencies of clock driven filter stage succeeding the intermediate stage having the selectable cutoff frequency are adjusted to eliminate staircasing distortion in the output signal. The filtered signal is then preferably passed through a fixed output filter to eliminate any frequency components at the clock rate of the last clock driven filter stage.

Claims

1. An electrical signal filter device having a selectable low pass cutoff frequency changeable within a designated range, said device comprising:

an input filter having an input node electrically connectable to receive input signals to be filtered, said input filter having a first fixed low pass cutoff frequency greater than an upper limit frequency of said designated range;

an output filter having an output node electrically connectable to deliver filtered output signals, said output filter having a second fixed low pass cutoff frequency greater than said upper limit frequency of said designated range;

at least three serially coupled clock driven filter stages electrically connected interposing said input filter and said output filter, each of said clock driven filter stages having a variable low pass cutoff frequency proportional to a clock rate of a respective clock signal applied thereto;

a first stage of said clock driven filter stages having a first variable low pass cutoff frequency no greater than said upper limit frequency of said designated range;

a second stage of said clock driven filter stages having a second variable low pass cutoff frequency no greater than said first variable low pass cutoff frequency and equal to said selectable low pass cutoff frequency;

a third stage of said clock driven filter stages having a third variable low pass cutoff frequency no less than said second variable low pass cutoff frequency and no greater than said second fixed low pass cutoff frequency; and

,

clock means for providing respective clock signals to said clock driven filter stages such that effective filtering of frequencies greater than said selectable low pass cutoff frequency is facilitated.

2. The electrical signal filter device of claim 1 wherein said at least serially coupled three clock driven filter stages comprises a plurality of N serially coupled clock driven filter stages, where N is an odd integer.

3. The electrical signal filter device of claim 2 wherein said variable low pass cutoff frequency of a middle stage of said N serially coupled clock driven filter stages is equal to said selectable low pass cutoff frequency.

4. The electrical signal filter device of claim 3 wherein stages of said N serially coupled clock driven filter stages preceding said middle stage have sequentially decreasing variable low pass cutoff frequencies and stages of said N serially coupled clock driven filter stages succeeding said middle stage have sequentially increasing variable low pass cutoff frequencies.

5. The electrical signal filter device of claim 4 wherein respective stages of said N serially coupled clock driven filter stages succeeding said middle stage have variable low pass cutoff frequencies equivalent to respective complementary stages of said N serially coupled clock driven filter stages preceding said middle stage.

6. The electrical signal filter device of claim 1 wherein said clock means comprises a single clock source and at least one frequency divider circuit.

7. The electrical signal filter device of claim 1 wherein said clock means comprises a plurality of clock sources.

8. A method of filtering frequency components of an electrical signal above a selectable low pass cutoff frequency changeable within a designated range, said method comprising the steps of:

(a) applying said electrical signal to a low pass input filter having a first fixed low pass cutoff frequency greater than an upper limit frequency of said designated range;

(b) applying an output of said low pass input filter to at least three serially coupled clock driven filter stages respectively having a variable low pass cutoff frequency proportional to a clock rate of a respective clock signal received applied thereto;

(c) adjusting the clock rate of said respective clock signal received as an input to a first stage of said at least three serially coupled clock driven filter stages to a frequency greater than twice said first fixed low pass cutoff frequency such that a first variable low pass cutoff frequency thereof is equal to said upper limit frequency of said designated range

(d) adjusting the clock rate of said respective clock signal received as an input to a second stage of said at least three serially coupled clock driven filter stages to a frequency greater than twice the variable low pass cutoff frequency of an immediately preceding stage of said clock driven filter stages such that a second variable cutoff frequency thereof is equal to said selectable low pass cutoff frequency; and

,

(e) adjusting the clock rate of said respective clock signal received as an input to a third stage of said at least three serially coupled clock driven filter stages such that a third variable cutoff frequency thereof is greater than said selectable low pass cutoff frequency and less than the clock rate of the respective clock signal applied to an immediately preceding stage.

9. The method of claim 8 further comprising the step of (f) applying an output of said third stage to a low pass output filter having a second fixed low pass cutoff frequency greater than said upper limit frequency of said designated range and less than the clock rate of the respective clock signal applied to said third stage.