Window tracking ADC

• US 5,296,856 A
• Filed: 03/04/1993
• Issued: 03/22/1994
• Est. Priority Date: 03/04/1993
• Status: Expired due to Fees

• Current Assignee: Mantong, Frank L.
• Original Assignee: Mantong, Frank L.
• Inventors: Mantong, Frank L.
• Primary Examiner(s): Young, Brian K.
• Application Number:
  US08/028,699
• Time in Patent Office: 383 Days
• Field of Search: 341/139, 341/122, 341/120, 341/155, 358/174
• US Class Current: 341/139
• CPC Class Codes: H03M 1/127 at intervals varying with the rate of change of the input signal

Abstract

A window tracking analog to digital convertor (10) and method of signal conversion is disclosed. A sample and hold amplifier (16) samples an analog input signal and passes the sampled signal to a window comparator (20). The window comparator (20) analyzes the analog input signal to determine if its amplitude falls between upper and lower reference levels which establish a tracking "window." If the amplitude of the signal falls outside of the window, a control processor (34) and window reference tracker (24) adjusts the reference levels in the direction of the reference level which was exceeded until the analog input signal falls within the window, the adjusted reference level in the direction of adjustment representing the level of the sampled signal. A continuous interval timer (38) counts the amount of time that the analog input signal remained within the window. Once the window is adjusted, a digital output signal represented by the amplitude of the sampled signal and the number of timing intervals is sent an instrument such as a computer for use.

Claims

1. A method of converting an analog input signal into a digital output signal, comprising the steps of:

(a) sampling an analog input signal to be converted, said analog input signal having an amplitude;

(b) comparing said amplitude of said sampled analog input signal to a voltage window defined by an upper reference voltage and a lower reference voltage;

(c) generating an out of limit signal in response to said amplitude of said sampled analog input signal falling outside said voltage window;

(d) adjusting, in response to said out of limit signal, said voltage window until said amplitude of said sampled analog input signal is within said voltage window;

(e) generating a plurality of periodic timing signals;

(f) counting said timing signals and generating a first output signal indicative of the number of timing signals occurring between said out of limit signal and an immediately preceding out of limit signal; and

(g) generating a second output signal indicative of said adjusted voltage window, said second output signal corresponding to said amplitude of said sampled analog input signal.

2. A method as recited in claim 1, further comprising the steps of:

(a) generating a first reference direction signal in response to said amplitude of said sampled analog input signal exceeding said upper reference voltage;

(b) generating a second reference direction signal in response to said amplitude of said sampled analog input signal falling below said lower reference voltage; and

(c) adjusting, in response to one of said reference direction signals, said voltage window in a direction corresponding to said one of said reference direction signals.

3. A method as recited in claim 2, wherein consecutive out of limit signals are separated by a time delay, and further comprising the step of comparing said time delay between consecutive out of limit signals to a predetermined time period and masking at least one of said out of limit signals in response to said predetermined time period exceeding said time delay.

4. A method as recited in claim 2, wherein said step of adjusting said voltage window comprises the step of adjusting said upper reference voltage and said lower reference voltage in tandem wherein a voltage differential between said reference voltages remains substantially constant.

5. A method as recited in claim 2, wherein said step of adjusting said voltage window comprises the step of independently adjusting said upper reference voltage and said lower reference voltage.

6. A method of analog to digital voltage signal conversion, comprising the steps of:

(a) comparing an analog voltage signal to an upper reference voltage;

(b) comparing said analog voltage signal to a lower reference voltage;

(c) in response to said analog voltage signal exceeding said upper reference voltage, generating an out of limit signal and increasing said upper reference voltage to a level at least equal to said analog voltage signal;

(d) in response to said lower reference voltage exceeding said analog voltage signal, generating an out of limit signal and decreasing said lower reference voltage to a level at least equal to said analog voltage signal;

(e) generating a plurality of periodic timing signals;

(f) counting said timing signals and generating a first output signal indicative of the number of timing signals occurring between consecutive out of limit signals; and

(g) generating a second output signal indicative of said adjusted upper and lower reference voltages, said second output signal corresponding to the amplitude of said analog input signal.

7. A method as recited in claim 6, wherein consecutive out of limit signals are separated by a time delay, and further comprising the step of comparing said time delay between consecutive out of limit signals to a predetermined time period and masking at least one of said out of limit signals in response to said predetermined time period exceeding said time delay.

8. A method as recited in claim 6, further comprising the steps of:

(a) adjusting said lower reference voltage in an amount and direction corresponding to adjustment of said upper reference voltage; and

(b) adjusting said upper reference voltage in an amount and direction corresponding to adjustment of said lower reference voltage.

9. An apparatus for converting an analog signal into digital form, comprising:

(a) signal sampling means for sampling an analog input signal to be converted, said analog signal having a voltage level;

(b) comparator means for comparing said analog input signal to a voltage window and generating an out of limit signal in response to said analog input signal having a voltage level outside said voltage window, said voltage window defined by an upper reference voltage and a lower reference voltage;

(c) reference tracker means for adjusting said voltage window until said voltage level of said analog input signal is within said window, said reference tracker means responsive to said out of limit signal;

(d) timer means for generating a plurality of periodic timing signals; and

(e) processor means for counting the number of timing signals occurring between consecutive out of limit signals and generating a first output signal indicative thereof and for generating a second output signal indicative of said voltage level of said analog input signal.

10. An apparatus as recited in claim 9, further comprising:

(a) means for generating a first reference direction signal in response to said voltage level of said analog input signal exceeding said upper reference voltage;

(b) means for generating a second reference direction signal in response to said voltage level of said analog input signal falling below said lower reference voltage; and

(c) means for adjusting, in response to one of said reference direction signals, said voltage window in a direction corresponding to said one of said reference direction signals.

11. An apparatus as recited in claim 10, further comprising means for adjusting said upper reference voltage and said lower reference voltage in tandem wherein a voltage differential between said reference voltages remains substantially constant.

12. An apparatus as recited in claim 10, wherein consecutive out of limit signals are separated by a time delay and further comprising means for comparing said time delay between said out of limit signal and an immediately preceding out of limit signal with a predetermined time period and masking at least one of said out of limit signals in response to said predetermined time period exceeding said time delay.

13. An analog to digital convertor, comprising:

(a) means for comparing an analog voltage signal to an upper reference voltage;

(b) means for comparing said analog voltage signal to a lower reference voltage;

(c) means for generating an out of limit signal and increasing said upper reference voltage to a level at least equal to said analog voltage signal in response to said analog voltage signal exceeding said upper reference voltage;

(d) means for generating an out of limit signal and decreasing said lower reference voltage to a level at least equal to said analog voltage signal in response to said lower reference voltage exceeding said analog voltage signal;

(e) means for generating a plurality of periodic timing signals;

(f) means for counting said timing signals and generating a first output signal indicative of the number of timing signals occurring between consecutive out of limit signals; and

(g) means for generating a second output signal indicative of said adjusted upper and lower reference voltages, said second output signal corresponding to the amplitude of said analog input signal.

14. An apparatus as recited in claim 13, wherein consecutive out of limit signals are separated by a time delay, and further comprising means for comparing said time delay between consecutive out of limit signals to a predetermined time period and masking at least one of said out of limit signals in response to said predetermined time period exceeding said time delay.

15. An apparatus as recited in claim 14, further comprising:

(a) means for adjusting said lower reference voltage in an amount and direction corresponding to adjustment of said upper reference voltage; and

(b) means for adjusting said upper reference voltage in an amount and direction corresponding to adjustment of said lower reference voltage.