Arithmetic circuit, and adaptive filter and echo canceler using it
First Claim
1. An arithmetic circuit comprising:
- a register for storing a predetermined data;
first data bus means, including a plurality of signal lines, and for transferring data;
memory means including,a plurality of word lines, data lines, and a plurality of memory cells for storing data,decoding means for selecting one word line from the plurality of word lines according to an address supplied, anddata input/output means to which the data lines are coupled, wherein the memory means outputs data from the memory cells coupled to the word line selected according to the address;
arithmetic means having a first input terminal for receiving the predetermined data from the register and a second input terminal for receiving data from the selected memory cells, the arithmetic means performing calculation on the data from the memory cells and the predetermined data from the register, the arithmetic means having an output terminal coupled to the memory means for outputting the calculation result, wherein the result of calculation by the arithmetic means is written from the output terminal of the arithmetic means into the memory cells coupled to the selected word line; and
data path means, including a plurality of signal lines, and for transferring data from the selected memory cells, wherein the data path means has a part dedicated only to transfer data from the selected memory cells to the second input terminal.
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Abstract
In the digital signal processor used for realizing application filters, the filter output calculation processing system 5 and the tap coefficient update calculation processing system 6 are separated. In the update calculation processing system 6, the integrating calculation for the tap coefficient updating that requires read and write operations on the data memory DRM is performed in one machine cycle by using the dedicated data bus 10 and executing the read-modify-write operation on the data memory. As a result, to the extent that the time taken by the integrating processing which has conventionally required two machine cycles can be shortened, the operation clock frequency can be lowered to reduce the power consumption while maintaining the processing capability per unit of time.
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Citations
20 Claims
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1. An arithmetic circuit comprising:
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a register for storing a predetermined data; first data bus means, including a plurality of signal lines, and for transferring data; memory means including, a plurality of word lines, data lines, and a plurality of memory cells for storing data, decoding means for selecting one word line from the plurality of word lines according to an address supplied, and data input/output means to which the data lines are coupled, wherein the memory means outputs data from the memory cells coupled to the word line selected according to the address; arithmetic means having a first input terminal for receiving the predetermined data from the register and a second input terminal for receiving data from the selected memory cells, the arithmetic means performing calculation on the data from the memory cells and the predetermined data from the register, the arithmetic means having an output terminal coupled to the memory means for outputting the calculation result, wherein the result of calculation by the arithmetic means is written from the output terminal of the arithmetic means into the memory cells coupled to the selected word line; and data path means, including a plurality of signal lines, and for transferring data from the selected memory cells, wherein the data path means has a part dedicated only to transfer data from the selected memory cells to the second input terminal. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A digital signal processor comprising:
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instruction memory means for storing instructions; instruction decode means for decoding instructions read from the instruction memory means to generate control signals; address generating means for generating addresses from the instructions read from the instruction memory means; and arithmetic means for performing arithmetic operations in accordance with the control signals and the addresses, the arithmetic means including, a register for storing a predetermined data, first data bus means, including a plurality of signal lines, and for transferring data; data memory means including, memory arrays including a plurality of word lines, data lines, and a plurality of memory cells for storing data, and data input/output means to which the data lines are coupled, wherein the memory means outputs data from the memory cells coupled to the word line selected according to the address; arithmetic unit having a first input terminal for receiving the predetermined data from the register and a second input terminal for receiving data from the selected memory cells, the arithmetic unit performing calculation on the data from the memory cells and the predetermined data from the register, the arithmetic unit having an output terminal coupled to the memory means for outputting the calculation result, wherein the result of calculation by the arithmetic unit is written from the output terminal of the arithmetic unit into the memory cells coupled to the selected word line; and data path means, including a plurality of signal lines, and of transferring data from the selected memory cells, wherein the data path means has a part dedicated only to transfer data from the selected memory cells to the second input terminal. - View Dependent Claims (8, 9, 10, 11, 12, 13)
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14. In a communication processing system comprising an analog-to-digital converter for converting analog signals into digital signals, a digital-to-analog converter for converting digital signals into analog signals, and a digital signal processor for receiving digital signals from the analog-to-digital converter and for performing digital signal processing on the signals;
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the digital signal processor including;
instruction memory means for storing instructions;instruction decode means for decoding instructions read from the instruction memory means to generate control signals; address generating means for generating addresses from the instructions read from the instruction memory means; and arithmetic means for performing arithmetic operations, in accordance with the control signals and the addresses, the arithmetic means including, a register for storing a predetermined data, data bus means, including a plurality of signal lines, and for transferring data; data memory means including, memory arrays including a plurality of word lines, data lines, a plurality of memory cells for storing data, decoding means for selecting one word line from the plurality of word lines according to the address supplied, and data input/output means to which the data lines are coupled, wherein the memory means outputs data from the memory cells coupled to the word line selected according to the address; arithmetic and logic unit having a first input terminal for receiving the predetermined data from the register and a second input terminal for receiving data from the selected memory cells, the arithmetic and logic unit performing calculation on the data from the memory cells and the predetermined data from the register, the arithmetic and logic unit having an output terminal coupled to the memory means for outputting the calculation result, wherein the result of calculation by the arithmetic and logic unit is written from the output terminal of the arithmetic and logic unit into the memory cells coupled to the selected word line; and data path means, including a plurality of signal lines, and for transferring data from the selected memory cells, wherein the data path means has a part dedicated only to transfer data from the selected memory cells to the second input terminal. - View Dependent Claims (15, 16, 17, 18, 19, 20)
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Specification