Arithmetic circuit, and adaptive filter and echo canceler using it

• US 5,297,071 A
• Filed: 02/28/1992
• Issued: 03/22/1994
• Est. Priority Date: 03/29/1991
• Status: Expired due to Fees

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Sugino, Kimihiro
• Primary Examiner(s): NGUYEN, LONG
• Application Number:
  US07/843,538
• Time in Patent Office: 753 Days
• Field of Search: 364/736, 364/724.01
• US Class Current: 708/322
• CPC Class Codes: G06F 15/7842 on one IC chip (single chip microcontrollers)
• CPC Class Codes: G06F 9/3001 Arithmetic instructions
• CPC Class Codes: H03H 2021/007 Computation saving measures; Accelerating measures
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

In the digital signal processor used for realizing application filters, the filter output calculation processing system 5 and the tap coefficient update calculation processing system 6 are separated. In the update calculation processing system 6, the integrating calculation for the tap coefficient updating that requires read and write operations on the data memory DRM is performed in one machine cycle by using the dedicated data bus 10 and executing the read-modify-write operation on the data memory. As a result, to the extent that the time taken by the integrating processing which has conventionally required two machine cycles can be shortened, the operation clock frequency can be lowered to reduce the power consumption while maintaining the processing capability per unit of time.

Claims

1. An arithmetic circuit comprising:

a register for storing a predetermined data;

first data bus means, including a plurality of signal lines, and for transferring data;

memory means including,

a plurality of word lines, data lines, and a plurality of memory cells for storing data,

decoding means for selecting one word line from the plurality of word lines according to an address supplied, and

data input/output means to which the data lines are coupled, wherein the memory means outputs data from the memory cells coupled to the word line selected according to the address;

arithmetic means having a first input terminal for receiving the predetermined data from the register and a second input terminal for receiving data from the selected memory cells, the arithmetic means performing calculation on the data from the memory cells and the predetermined data from the register, the arithmetic means having an output terminal coupled to the memory means for outputting the calculation result, wherein the result of calculation by the arithmetic means is written from the output terminal of the arithmetic means into the memory cells coupled to the selected word line; and

data path means, including a plurality of signal lines, and for transferring data from the selected memory cells, wherein the data path means has a part dedicated only to transfer data from the selected memory cells to the second input terminal.

2. The arithmetic circuit according to claim 1, wherein the number of signal lines in the first data bus means is smaller than that of signal lines in the data path means.

3. The arithmetic circuit according to claim 2, further comprising shift means, which is coupled between the first data bus means and the first input terminal through second data bus means, the second data bus means having the same number of signal lines as the data path means, and which shifts data from the first data bus means and outputs the shifted data onto the second data bus means.

4. The arithmetic circuit according to claim 3, further comprising coupling means for coupling the data path means to the first data bus means, wherein the coupling means outputs data from the data path means onto the first data bus means.

5. The arithmetic circuit according to claim 4, wherein the coupling means are provided one for each signal line making up the first data bus means, and the signal lines of the data path means are coupled through the coupling means to the signal lines of the first data bus means beginning with the most significant bit of the data read out from the memory means.

6. The arithmetic circuit according to claim 5, further comprising second arithmetic means for performing calculation on the data output from the coupling means onto the first data bus means and on predetermined data.

7. A digital signal processor comprising:

instruction memory means for storing instructions;

instruction decode means for decoding instructions read from the instruction memory means to generate control signals;

address generating means for generating addresses from the instructions read from the instruction memory means; and

arithmetic means for performing arithmetic operations in accordance with the control signals and the addresses, the arithmetic means including,

a register for storing a predetermined data,

first data bus means, including a plurality of signal lines, and for transferring data;

data memory means including,

memory arrays including a plurality of word lines, data lines, and a plurality of memory cells for storing data, and

data input/output means to which the data lines are coupled, wherein the memory means outputs data from the memory cells coupled to the word line selected according to the address;

arithmetic unit having a first input terminal for receiving the predetermined data from the register and a second input terminal for receiving data from the selected memory cells, the arithmetic unit performing calculation on the data from the memory cells and the predetermined data from the register, the arithmetic unit having an output terminal coupled to the memory means for outputting the calculation result, wherein the result of calculation by the arithmetic unit is written from the output terminal of the arithmetic unit into the memory cells coupled to the selected word line; and

data path means, including a plurality of signal lines, and of transferring data from the selected memory cells, wherein the data path means has a part dedicated only to transfer data from the selected memory cells to the second input terminal.

8. The digital signal processor according to claim 7, wherein the number of signal lines of the first data bus means is smaller than that of signal lines of the data path means.

9. The digital signal processor according to claim 8, further comprising shift means, which is coupled between the first data bus means and the first input terminal through second data bus means, the second data bus means having the same number of signal lines as the data path means, and which shifts data from the first data bus means and outputs the shifted data onto the second data bus means.

10. The digital signal processor according to claim 9, further comprising coupling mans for coupling the data path means to the first data bus means, wherein the coupling mans outputs data from the data path means onto the first data bus means.

11. The digital signal processor according to claim 10, wherein the coupling means are provided one for each signal line making up the first data bus means, and the signal lines of the data path means are coupled through the coupling means to the signal lines of the first data bus means beginning with the most significant bit of the data read out from the memory means.

12. The digital signal processor according to claim 11, further comprising second arithmetic means for performing calculation on the data output from the coupling means onto the first data bus means and on predetermined data.

13. The digital signal processor according to claim 12, wherein the digital signal processor is formed on a single semiconductor chip.

14. In a communication processing system comprising an analog-to-digital converter for converting analog signals into digital signals, a digital-to-analog converter for converting digital signals into analog signals, and a digital signal processor for receiving digital signals from the analog-to-digital converter and for performing digital signal processing on the signals;

the digital signal processor including;

instruction memory means for storing instructions;

instruction decode means for decoding instructions read from the instruction memory means to generate control signals;

address generating means for generating addresses from the instructions read from the instruction memory means; and

arithmetic means for performing arithmetic operations, in accordance with the control signals and the addresses, the arithmetic means including,

a register for storing a predetermined data,

data bus means, including a plurality of signal lines, and for transferring data;

data memory means including,

memory arrays including a plurality of word lines, data lines,

a plurality of memory cells for storing data,

decoding means for selecting one word line from the plurality of word lines according to the address supplied, and

data input/output means to which the data lines are coupled, wherein the memory means outputs data from the memory cells coupled to the word line selected according to the address;

arithmetic and logic unit having a first input terminal for receiving the predetermined data from the register and a second input terminal for receiving data from the selected memory cells, the arithmetic and logic unit performing calculation on the data from the memory cells and the predetermined data from the register, the arithmetic and logic unit having an output terminal coupled to the memory means for outputting the calculation result, wherein the result of calculation by the arithmetic and logic unit is written from the output terminal of the arithmetic and logic unit into the memory cells coupled to the selected word line; and

data path means, including a plurality of signal lines, and for transferring data from the selected memory cells, wherein the data path means has a part dedicated only to transfer data from the selected memory cells to the second input terminal.

15. The communication processing system according to claim 14, wherein the number of signal lines of the data bus means is smaller than that of signal lines of the data path means.

16. The communication processing system according to claim 15, wherein the digital signal processor is formed on a single semiconductor chip.

17. The communication processing system according to claim 16, wherein the arithmetic and logic unit has coupling means for coupling the data path means to the data bus means, and the coupling means outputs data from the data path means onto the data bus means.

18. The communication processing system according to claim 17, wherein the coupling means are provided one for each signal line making up the data bus mans, and the signal lines of the data path means are coupled through the coupling means to the signal lines of the data bus means beginning with the most significant bit of the data read out from the memory means.

19. The communication processing system according to claim 18, wherein the arithmetic and logic unit has second arithmetic and logic unit for performing calculation on the data output from the coupling means onto the data bus means and on predetermined data.

20. The communication processing system according to claim 19, wherein the digital signal processor cancels echo components supplied from the analog-to-digital convertor by the output data of the second arithmetic and logic unit.