System and method for bit timing synchronization in an adaptive direct sequence CDMA communication system

• US 5,297,162 A
• Filed: 06/04/1993
• Issued: 03/22/1994
• Est. Priority Date: 06/04/1993
• Status: Expired due to Term

• Current Assignee: Motorola Solutions, Inc.
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Babayi, Robert S., Cadd, Jimmy, Fulghum, Tracy L., Lee, Edward K. B.
• Primary Examiner(s): Cain, David C.
• Application Number:
  US08/073,226
• Time in Patent Office: 291 Days
• Field of Search: 375/1, 380/48, 380/49
• US Class Current: 375/143
• CPC Class Codes: H04B 1/7097 Interference-related aspects
• CPC Class Codes: H04J 13/00 Code division multiplex systems for frequency hopping H04B1/713
• CPC Class Codes: H04L 7/041 using special codes as synchronising signal
• CPC Class Codes: H04L 7/046 using a dotting sequence

Abstract

In a CDMA communication system (100) capable of communicating between a receiver (20) and a transmitter (10) direct sequence spread spectrum communication signals (30), a system and method for synchronizing receiver bit timing and transmitter timing. Transmitter (10) transmits a training bit sequence (31) followed by a transmitter bit timing sequence (33). The receiver (20) adaptively determines a representation of a despreading chip sequence using a tapped delay line equalizer (400). Receiver bit timing offset is determined based on the representation of the despreading chip sequence and the transmitter bit timing sequence (33).

Claims

1. In a direct sequence CDMA spread spectrum communication system, wherein spread spectrum communication signals comprising binary bits coded with spreading chip sequences are communicated between a transmitter and a receiver;

a bit synchronization method for synchronizing receiver bit timing with transmitter bit timing comprising the steps of;

a) transmitting a direct sequence spread spectrum communication signal (DS-SS) including a redundant training bit sequence followed by a transmitter bit timing sequence coded with a spreading chip sequence;

b) despreading the DS-SS communication signal based on said redundant training bit sequence to provide a decoded communication signal; and

c) determining receiver bit timing offset based on the transmitter bit timing sequence and the decoded communication signal.

2. The method of claim 1, wherein said step of despreading the DS-SS communication signal includes the step of:

adaptively determining a representation of despreading chip sequence using an equalizer.

3. The method of claim 2, wherein the DS-SS communication signal includes consecutive non-alternating bits and the transmitter bit timing sequence comprises alternating bits wherein the state of at least one of two consecutive bits is changed from one bit interval to the succeeding bit interval.

4. The method of claim 3, wherein said step of determining bit timing offset includes the steps of:

integrating the decoded communication signal over a receiver bit interval during alternating bits.

5. The method of claim 4, wherein said step of determining bit timing offset includes the steps of:

producing integration of the decoded communication signal over a receiver bit interval during the consecutive non-alternating bits; and

determining sign of the bit timing offset by comparing results of integrations produced during consecutive non-alternating bits with that obtained during alternating bits.

6. In a direct sequence CDMA receiver system capable of receiving spread spectrum communication signals comprising binary bits coded with a spreading chip sequence from a transmitter;

a bit synchronization method for synchronizing receiver bit timing with transmitter bit timing comprising the steps of;

a) receiving a redundant training bit sequence;

b) despreading the DS-SS communication signal based on said redundant training bit sequence to provide a decoded communication signal;

c) receiving a transmitter bit timing sequence; and

d) determining receiver bit timing offset based on the transmitter bit timing sequence and the decoded communication signal.

7. The method of claim 6, wherein said step of despreading the DS-SS communication signal includes the step of:

adaptively determining a representation of despreading chip sequence using an equalizer.

8. The method of claim 7, wherein the decoded communication signal includes consecutive non-alternating bits and the transmitter bit timing sequence includes alternating bits wherein the state of at least one of two consecutive bits is changed from one bit interval to the succeeding bit interval.

9. The method of claim 8, wherein said step of determining chip timing offset includes the steps of:

integrating the decoded communication signal over a first receiver bit interval during the consecutive non-alternating bits to produce a first result; and

integrating the decoded communication signal over a second receiver bit interval during alternating bits to produce a second result.

10. The method of claim 9, wherein said step of determining chip timing offset includes the steps of:

determining sign of the bit timing offset by comparing results of integrations produced during consecutive non-alternating bits with that obtained during alternating bits.

11. A CDMA communication system for communicating direct sequence spread spectrum communication signals comprising:

a transmitter for transmitting a direct sequence spread spectrum (DS-SS) communication signal including a redundant training bit sequence followed by a transmitter bit timing sequence coded with a spreading chip sequence;

a receiver for receiving said DS-SS communication signal including;

despreading means for despreading the DS-SS communication signal based on said redundant training bit sequence and providing a decoded communication signal; and

determination means for determining receiver bit timing offset based on said decoded communication signal and said transmitter bit timing sequence.

12. The communication system of claim 11, wherein said despreading means comprises an equalizer for adaptively determining a representation of a despreading chip sequence.

13. The communication system of claim 12, wherein the decoded communication signal includes consecutive non-alternating bits and the transmitter bit timing sequence includes alternating bits wherein the state of at least one of two consecutive bits is changed from one bit interval to the succeeding bit interval.

14. The communication system of claim 13, wherein said equalizer includes a summer for integrating the decoded communication signal over a first receiver bit interval during the consecutive non-alternating bits to produce a first result and for integrating the decoded communication signal over a second receiver bit interval during alternating bits to produce a second result.

15. The communication system of claim 13, wherein said determination means includes means for determining sign of the bit timing offset by comparing the first result with the second result.

16. A direct sequence CDMA receiver, comprising:

means for receiving a direct sequence spread spectrum communication signal including a redundant training bit sequence followed by a transmitter bit timing sequence coded with a spreading chip sequence;

a despreading means for despreading the DS-SS communication signal based on said redundant training bit sequence and providing a decoded communication signal; and

determination means for determining receiver bit timing offset based on said decoded communication signal and said transmitter bit timing sequence.

17. The receiver of claim 16, wherein said wherein said despreading means comprise an equalizer for adaptively determining a representation of a despreading chip sequence.

18. The receiver of claim 17, wherein the decoded communication signal includes consecutive non-alternating bits and the transmitter bit timing sequence includes alternating bits wherein the state of at least one of two consecutive bits is changed from one bit interval to the succeeding bit interval.

19. The receiver of claim 18, wherein said equalizer includes a summer for integrating the decoded communication signal, over a first receiver bit interval, during the consecutive non-alternating bits to produce a first result and for integrating the decoded communication signal, over a second receiver bit interval, during alternating bits to produce a second result.

20. The receiver of claim 19, wherein said determination means includes means for determining sign of the bit timing offset by comparing the first result with the second result.