Apparatus for automatically disabling and isolating a computer's original processor upon installation of a processor upgrade card

• US 5,297,272 A
• Filed: 08/02/1989
• Issued: 03/22/1994
• Est. Priority Date: 08/02/1989
• Status: Expired due to Term

• Current Assignee: AD Technologies LLC
• Original Assignee: Advanced Logic Research, Inc. (Acer, Inc.)
• Inventors: Kelly, David L., Hack, Norman M., Rushford, Scott R., Lu, Gene Y.
• Primary Examiner(s): Lall, Parshotam S.
• Assistant Examiner(s): Ellis, Richard Lee
• Application Number:
  US07/388,445
• Time in Patent Office: 1,693 Days
• Field of Search: 364/200 MS File, 364/900 MS File, 395/800, 395/500
• US Class Current: 710/301
• CPC Class Codes: G06F 13/4063 Device-to-bus coupling

Abstract

A system and method for upgrading a computer is disclosed. Certain essential chips present in the original computer system are functionally, but not physically, removed from the computer system. The functions which would otherwise be performed by the original chips are instead performed by higher-performance chips on a plug-in module which is plugged into the computer system. The functional removal of the certain chips from the original computer system is achieved through simple insertion of the plug-in module. No replacement or substitution of original chips or boards is necessary.

Claims

1. An upgraded computer system, comprising:

1) a system board including at least a part of a first chip set, the first chip set including;

a) an 80286 processor chip having a HOLD input, the 80286 processor chip having status and control signals of an 80286 timing and format;

b) an 82C211 chip; and

c) a numeric processor interrupt disable circuit, receiving an interrupt signal from the 82C211 chip;

2) an 80386SX plug-in module including;

a) an 80386SX processor socket in which is inserted an 80386SX processor chip, the 80386SX processor chip having status and control signals of an 80386SX timing and format;

b) an 80387SX co-processor socket;

c) translation circuitry which translates status and control signals from the 80386SX timing and format to the 80286 timing and format, the translation circuitry including programmable arrays of logic elements whose composite function is determined by programming a plurality of equations thereinto;

d) a numeric processor interrupt circuit which generates a plug-in numeric processor interrupt signal under certain conditions;

e) a first clock selection circuit which determines the characteristics of clock signal which is used by clock generation circuitry within the 82C211 chip; and

f) an installation announcement circuit, the installation announcement circuit including a connection from an SXINST# pin on a plug-in connector to ground, the connection from the SXINST# to ground providing an installation announcement signal to which the 80286 processor is responsive whenever the plug-in module is installed, the installation announcement signal causing disablement of the 82086 processor without its physical removal from the system board while allowing the 80386SX processor to assume functions in the computer system otherwise performed by the 80286 processor, the installation announcement signal also causing the numeric processor interrupt disable circuit to prevent the interrupt signal from the 82C211 from reaching any portion of the computer system; and

3) a connector, in electrical contact with both the system board and the installed plug-in module, for carrying the SXINST# signal from the installation announcement circuit on the 80386SX plug-in module to control the HOLD input of the 80286 processor and the numeric processor interrupt disable circuit on the system board.

2. The upgraded computer system of claim 1, wherein:

the installation announcement circuit includes a conductive pathway, and includes no active circuit elements.

3. A base computer system with modular upgrade capability, in which installation of a module which is not originally part of the base computer system causes functional disablement of a first processor without its physical removal from the computer system, while allowing a second processor on the module to assume functions which would otherwise be performed by the first processor, the base computer system having an expansion bus with a set of expansion bus signal paths, the base computer system comprising:

a) the first processor, having a first input which, when activated, disables the first processor;

b) an OR circuit having an output signal which is input to the first input of the first processor, the OR circuit having respective inputs responsive to;

1) a first signal generated from within the base computer system, the first signal for causing functional disablement of the first processor when the first signal is active and a module is not installed in the base computer system; and

2) an installation announcement signal output by the module when the module is installed, the installation announcement signal being restricted to a path in the base computer system which is electrically separate from the expansion bus signals paths, thereby causing functional disablement only of the first processor and of minimal portions of the base computer system to allow the second processor to assume functions otherwise performed by the first processor; and

c) the path which carries the installation announcement signal to the OR circuit.

4. The base computer system of claim 3, wherein the first processor has a first output which, when activated, acknowledges disablement of the first processor, the system further comprising:

c) an acknowledgement isolation circuit, including;

1) an input responsive to the first output of the first processor;

2) an output which may either be

i) responsive to the first output of the first processor;

or

ii) rendered inactive; and

3) an enable input responsive to the installation announcement signal for controlling whether the output of the acknowledgement isolation circuit is responsive to the first output of the first processor or whether it is rendered inactive.

5. The system of claim 3, wherein:

the first processor is part of a first integrated circuit chip; and

the OR circuit is separate from the first integrated circuit chip.

6. The system of claim 3, wherein:

the first processor is part of a first integrated circuit chip; and

the OR circuit is part of a second integrated circuit chip which is separate from the first integrated circuit chip.

7. The system of claim 3, wherein:

the OR circuit employs a negative logic in which any "O" input signal causes the output of the OR circuit to be active.

8. The system of claim 3, wherein:

the first input of the first processor is an input which, when activated, does not disable the first processor until the end of a current instruction cycle.

9. The system of claim 3, wherein:

the first input of the first processor is an input which, when activated, causes the first processor to activate a hold acknowledge output signal.

10. A base computer system with modular upgrade capability, in which installation of a module which is not originally part of the base computer system causes functional disablement of at least a portion of the base computer system without its physical removal from the computer system, while allowing the module to assume functions which would otherwise be performed by the disabled portions of the base computer system, the module generating an installation announcement signal when installed in the base computer system, the base computer system comprising:

a) a circuit which generates a local numeric processor interrupt signal;

b) a numeric processor interrupt isolation circuit, including;

1) an input responsive to the local numeric processor interrupt signal;

2) an output which may either be

i) responsive to the local numeric processor interrupt signal;

or

ii) rendered inactive; and

3) an enable input, responsive to the installation announcement signal from the module, the enable input controlling whether the output of the numeric processor interrupt isolation circuit (i) is responsive to the local numeric processor interrupt signal or (ii) is rendered inactive.

11. A base computer system with modular upgrade capability, in which installation of a module which is not originally part of the base computer system cause disablement of a first processor without its physical removal from the computer system, so as to allow a second processor on the module to assume functions otherwise performed by the first processor, the base computer system having an expansion bus with a set of expansion bus signal paths, the base computer system comprising:

a) the first processor, having a first input which, when activated, disables the first processor;

b) an OR circuit having an output signal which is input to the first input of the first processor, the OR circuit having respective inputs responsive to;

1) a first signal generated from within the base computer system, the first signal for causing disablement of the first processor when the first signal is active and a module is not installed in the base computer system; and

2) an installation announcement signal which is generated when the module is installed into the base computer system, the installation announcement signal being restricted to a path in the base computer system which is electrically separate from the expansion bus signal paths, thereby causing functional disablement only of the first processor and of minimal portions of the base computer system to allow the second processor to assume functions otherwise performed by the first processor; and

c) the path which carries the installation announcement signal to the OR circuit.

12. The system of claim 11, wherein:

the first processor is part of a first integrated circuit chip; and

the OR circuit is separate from the first integrated circuit chip.

13. The system of claim 11, wherein:

the first processor is part of a first integrated circuit chip; and

the OR circuit is part of a second integrated circuit chip which is separate from the first integrated circuit chip.

14. The system of claim 11, wherein:

the OR circuit employs a negative logic in which any "O" signal causes the output of the OR circuit to be active.

15. The system of claim 11, wherein:

the first input of the first processor is an input which, when activated, does not disable the first processor until the end of a current instruction cycle.

16. The system of claim 11, wherein:

the first input of the first processor is an input which, when activated, causes the first processor to activate a hold acknowledge output signal.

17. A base computer system with modular upgrade capability, in which installation of a module which is not originally part of the base computer system causes disablement of a first processor without its physical removal from the computer system, so as to allow a second processor on the module to assume functions otherwise performed by the first processor, the base computer system having an expansion bus with a set of expansion bus signal paths, the base computer system comprising:

a) the first processor, having a first input which, when activated, disables the first processor;

b) means for providing a disabling signal to the first input of the first processor, in response to (1) a first signal generated from within the base computer system, the first signal causing disablement of the first processor when the first signal is active and a module is not installed in the base computer system, or (2) an installation announcement signal output by the module when the module is installed into the base computer system, the installation announcement signal thereby causing functional disablement of the first processor so as to allow the second processor to assume functions otherwise performed by the first processor, wherein the means for providing the disabling signal constitutes means for providing the disabling signal only to the first processor and to portions of the base computer system other than the expansion bus, which portions if not disabled would interfere with the second processor'"'"'s assuming functions otherwise performed by the first processor; and

c) a path for carrying the installation announcement signal to the means for providing, the path being electrically separate from the expansion bus signal paths.

18. The system of claim 17, wherein:

the first processor is part of the first integrated circuit chip; and

the providing means is separate form the first integrated circuit chip.

19. The system of claim 17, wherein:

the first processor is part of a first integrated circuit chip; and

the providing means is part of a second integrated circuit chip which is separate from the first integrated circuit chip.

20. The system of claim 17, wherein:

the providing means employs a negative logic in which any "O" input signal causes the output of the providing means to be active.

21. The system of claim 17, wherein:

the first input of the first processor is an input which, when activated, does not disable the first processor until the end of a current instruction cycle.

22. The system of claim 17, wherein:

the first input of the first processor is an input which, when activated, causes the first processor to activate a hold acknowledge output signal.

23. An upgraded computer system having an expansion bus with a set of expansion bus signal paths, the upgraded computer system comprising:

1) a first processor having a first input which, when activated, disables the first processor;

2) a module including;

a) a second processor, having at least certain performance characteristics different than performance characteristics of the first processor; and

b) an installation announcement circuit for generating an installation announcement signal whenever the module is installed in the computer system, the first input of the first processor being responsive to the installation announcement signal to cause disablement of the first processor without its physical removal from the computer system, the installation announcement signal not causing disablement of any portion of the computer system other than the first processor and portions of the computer system which if not disabled would interfere with the second processor'"'"'s assuming functions otherwise performed by the first processor; and

3) a path, being electrically separate from the expansion bus signal paths, for carrying the installation announcement signal from the module only to the processor and to the portions which if not disabled would interfere with the second processor'"'"'s assuming functions otherwise performed by the first processor;

wherein the installation announcement circuit generates the installation announcement signal to cause disablement of (1) a disable acknowledge signal indicating disablement of the first processor to the remainder of the computer system, as well as (2) a co-processor interrupt which, if not disabled, would interfere with the operation of the second processor.

24. The computer system of claim 23, wherein the first input is a HOLD input.

25. The upgraded computer system of claim 23, wherein:

the installation announcement circuit is located outside an integrated circuit chip in which the second processor is located.

26. The upgraded computer system of claim 23, wherein the installation announcement circuit includes:

a short circuit pathway extending between (1) a predetermined constant signal level and (2) a pathway to which the first input of the first processor is responsive.

27. The upgraded computer system of claim 26, wherein the installation announcement circuit consists essentially of:

a short circuit pathway extending between (1) ground and (2) a pathway to which the first input of the first processor is responsive.

28. The upgraded computer system of claim 23, wherein:

the first processor has associated therewith a first bus with first bus characteristics;

the second processor has associated therewith a second bus with second bus characteristics; and

the module includes means to ensure full compatibility between the first bus characteristics and the second bus characteristics.

59. The upgraded computer system of claim 24, wherein:

the installation announcement circuit is located outside an integrated circuit chip in which the second processor is located.

60. The upgraded computer system of claim 24, wherein:

the installation announcement circuit includes;

a short circuit pathway extending between (1) a predetermined constant signal level and (2) a pathway to which the first input of the first processor is responsive.

61. The upgraded computer system of claim 60, wherein the installation announcement circuit consists essentially of:

a short circuit pathway extending between (1) ground and (2) a pathway to which the first input of the first processor is responsive.

62. The upgraded computer system of claim 24, wherein:

the first processor has associated therewith a first bus with first bus characteristics;

the second processor has associated therewith a second bus with second bus characteristics; and

the module includes means to ensure full compatibility between the first bus characteristics and the second bus characteristics.

29. A base computer system with modular upgrade capability, in which installation of a module which is not originally part of the base computer system caused disablement of a first processor without its physical removal from the computer system, while allowing a second processor on the module to assume functions which would otherwise be performed by the first processor, the base computer system having an expansion bus with a set of expansion bus signal paths, the base computer system comprising:

a) the first processor, having a first input which, when activated, disables the first processor;

b) means for providing a disabling signal to the first input of the first processor, in response to (1) a first signal generated from within the base computer system, the first signal for causing disablement of the first processor when the first signal is active and a module is not installed in the base computer system, for (2) an installation announcement signal output by the module whenever it is installed in the base computer system;

c) means for disabling signals generated in the base computer system (`b) which, if not disabled, would indicate disablement of the first processor to the remainder of the base computer system or (2) which, if not disabled, would interfere with control exerted by the module; and

d) a path for carrying the installation announcement signal to the means for providing and to the means for disabling, the path being electrically separate from the expansion bus signal paths.

30. The base computer system of claim 29, wherein the first input is a HOLD input.

31. The base computer system of claim 29, wherein the installation announcement circuit generates the installation announcement signal to cause disablement of (1) any disable acknowledge signal associated with the first processor as well as (2) any co-processor interrupts, which would otherwise interfere with the operation of the second processor.

32. The base computer system of claim 29, wherein the first processor has a first output which, when activated, acknowledges disablement of the first processor, the system further comprising:

c) an acknowledgement isolation circuit, including;

1) an input responsive to the first output of the first processor;

2) an output which may either be

i) responsive to the first output of the first processor;

or

ii) rendered inactive; and

3) an enable input responsive to the installation announcement signal for controlling whether the output of the acknowledgement isolation circuit is responsive to the first output of the first processor or whether it is rendered inactive.

33. The system of claim 29, wherein:

the first processor is part of a first integrated circuit chip; and

the providing means is separate from the first integrated circuit chip.

34. The system of claim 29, wherein:

the first processor is part of a first integrated circuit chip; and

the providing means is part of a second integrated circuit chip which is separate from the first integrated circuit chip.

35. The system of claim 29, wherein:

the providing means employs a negative logic in which any "O" input signal causes the output of the providing means to be active.

36. The system of claim 29, wherein:

the first input of the first processor is an input which, when activated, does not disable the first processor until the end of a current instruction cycle.

37. The system of claim 29, wherein:

the first input of the first processor is an input which, when activated, causes the first processor to activate a hold acknowledge output signal.

38. An upgraded computer system having an expansion bus with a set of expansion bus signal paths, the upgraded computer system comprising:

1) a first processor having a first input which, when activated, disables the first processor;

2) a module installed in the computer system, the module including a second processor and an installation announcement circuit for generating an installation announcement signal whenever the module is installed in the computer system;

3) a first path, being electrically separate from the expansion bus signal paths, for carrying to the first input a disabling signal determined by the installation announcement signal so that installation of the module causes disablement of the first processor without its physical removal from the computer system, the first path carrying the disabling signal leading only to portions of the computer system which, if not disabled, would interfere with the second processor'"'"'s assuming functions otherwise performed by the first processor; and

4) a second path, being electrically separate from the expansion bus signal paths, for carrying the installation announcement signal from the module to activate the disabling signal;

wherein the installation announcement circuit generates the installation announcement signal to cause disablement of (1) a disable acknowledge signal indicating disablement of the first processor to the remainder of the computer system, as well as (2) a co-processor interrupt which, if not disabled, would interfere with the operation of the second processor.

39. The upgraded computer system of claim 38, wherein the first input is a HOLD input.

40. The upgraded computer system of claim 38, wherein:

the installation announcement circuit is located outside an integrated circuit chip in which the second processor is located.

41. The upgraded computer system of claim 38, wherein the installation announcement circuit includes:

a short circuit pathway extending between (1) a predetermined constant signal level and (2) a pathway in which the first input of the first processor is responsive.

42. The upgraded computer system of claim 41, wherein the installation announcement circuit includes:

a short circuit pathway extending between (1) ground and (2) a pathway to which the first input of the first processor is responsive.

43. The upgraded computer system of claim 38, wherein:

the first processor has associated therewith a first bus with first bus characteristics;

the second processor has associated therewith a second bus with second bus characteristics; and

the module includes means to ensure full compatibility between the first bus characteristics and the second bus characteristics.

44. A base computer system with modular upgrade capability, in which installation of a module which is not originally part of the base computer system causes disablement of a first processor without its physical removal from the computer system, so as to allow a second processor on the module to assume functions otherwise performed by the first processor, the base computer system having an expansion bus with a set of expansion bus signal paths, the base computer system comprising:

a) the first processor, having a first input which, when activated, disables the first processor;

b) means for providing a disabling signal to the first input of the first processor, in response to;

(1) a first signal generated from within the base computer system, the first signal causing disablement of the first processor when the first signal is active and a module is not installed in the base computer system, or

(2) an installation announcement signal generated by the module whenever the module is installed in the base computer system so as to cause disablement of the first processor and allow the second processor to assume functions otherwise performed by the first processor;

c) means for disabling signals generated in the base computer system (1) which, if not disabled, would indicate disablement of the first processor to the remainder of the base computer system or (2) which, if not disabled, would interfere with control exerted by the module; and

d) a path for carrying the installation announcement signal to the means for providing and to the means for disabling, the path being electrically separate from the expansion bus signal paths.

45. The base computer system of claim 44, wherein the first input is a HOLD input.

46. The base computer system of claim 44, wherein the means for disabling includes:

means for disabling (1) any disable acknowledge signal associated with the first processor as well as (2) any co-processor interrupts, which would otherwise interfere with the operation of the second processor.

47. The system of claim 44, wherein:

the first processor is part of a first integrated circuit chip; and

the providing means is separate from the first integrated circuit chip.

48. The system of claim 44, wherein:

the first processor is part of a first integrated circuit chip; and

the providing means is part of a second integrated circuit chip which is separate from the first integrated circuit chip.

49. The system of claim 44, wherein:

the providing means employs a negative logic in which any "O" input signal causes the output of the providing means to be active.

50. The system of claim 44, wherein:

the first input of the first processor is an input which, when activated, does not disable the first processor until the end of a current instruction cycle.

51. The system of claim 44, wherein:

the first input of the first processor is an input which, when activated, causes the first processor to activate a hold acknowledge output signal.

52. A base computer system with modular upgrade capability, in which installation of a module which is not originally part of the base computer system causes disablement of a first processor without its physical removal from the computer system, so as to allow a second processor on the module to assume functions otherwise performed by the first processor, the base computer system having an expansion bus with a set of expansion bus signal paths, the base computer system comprising:

a) the first processor, having a first input which, when activated, disables the first processor;

b) a first path for carrying to the first input a disabling signal determined by an installation announcement signal which is generated whenever the module is installed in the base computer system, the first path leading only to the first processor and portions of the computer system which, if not disabled, would interfere with the second processor'"'"'s assuming functions otherwise performed by the first processor; and

c) a second path, electrically separate from the expansion bus signal paths, for carrying the installation announcement signal from the module to activate the disabling signal;

wherein the first path, leads only to the first processor, to disable acknowledge signal gating means associated with the first processor, and to co-processor interrupt gating means, which, if not disabled, would interfere with the operation of the second processor.

53. The base computer system of claim 52, wherein the first input is a HOLD input.

54. The base computer system of claim 52, wherein:

the installation announcement signal is a predetermined constant signal level provided to a first pin on a connector to the module, the first pin being adjacent a pin which receives the installation announcement signal from the module.

55. The base computer system of claim 54, wherein:

the predetermined constant signal level is ground, the installation announcement signal constituting a short circuit to ground when the module is installed in the base computer system.

56. An upgraded computer system, comprising:

1) a first processor having a first input which, when activated, disables the first processor; and

2) a module consisting essentially of;

a) a second processor and any related co-processor, having at least certain performance characteristics different than performance characteristics of the first processor;

b) an installation announcement circuit for generating an installation announcement signal when the module is installed in the computer system, the first input of the first processor being responsive to the installation announcement signal to cause disablement of the first processor without its physical removal from the computer system, the installation announcement signal not causing disablement of any portion of the computer system other than the first processor and portions of the computer system which, if not disabled, would interfere with the second processor'"'"'s assuming functions otherwise performed by the first processor;

c) translation circuitry making a bus of the first processor compatible with a bus of the second processor; and

d) means for allowing the second processor, installation announcement circuit, and translation circuitry to operate properly;

wherein the installation announcement circuit generates the installation announcement signal to cause disablement of (1) a disable acknowledge signal indicating disablement of the first processor to the remainder of the computer system as well as (2) a co-processor interrupt which, if not disabled, would interfere with the operation of the second processor.

57. The computer system of claim 56, wherein:

the module'"'"'s second processor is an integrated circuit chip; and

the module has no cache memory outside the integrated circuit chip.

58. The computer system of claim 56, wherein:

the translation circuit includes arrays of logic elements which are responsive to signals on the respective busses of the first and second processors and which provide other signals to the respective busses of the first and second processors.

63. The upgraded computer system of claim 56, wherein the means for allowing includes:

a power bus;

a ground bus;

a circuit board providing support for the foregoing elements;

a connector on an edge of the circuit board; and

conductive pathways interconnecting the foregoing elements.