Bus system wherein a bus-using request signal is issued in advance of a determination that a bus is to be used and is thereafter cancelled if the bus is not used

• US 5,297,292 A
• Filed: 05/13/1991
• Issued: 03/22/1994
• Est. Priority Date: 05/11/1990
• Status: Expired due to Fees

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Endo, Norikazu, Morimoto, Shigeki, Nakauchi, Toshihiko
• Primary Examiner(s): Ray, Gopal C.
• Application Number:
  US07/698,956
• Time in Patent Office: 1,044 Days
• Field of Search: 364/DIG. 1 MS File, 364/DIG. 2 MS File, 395/325, 395/725, 395/200, 340/825.5, 370/85.2
• US Class Current: 710/113
• CPC Class Codes: G06F 13/36 for access to common bus or bus system
• CPC Class Codes: G06F 13/3625 using a time dependent access
• CPC Class Codes: G06F 15/17 using an input/output type connection, e.g. channel, I/O port

Abstract

A method is provided for controlling bus-using rights in a multi-bus system which has a plurality of buses and a plurality of units connected to each of the buses. A unit connected to one bus is accessible by another unit connected to another bus. When a first unit accesses either a second unit on the one bus or a third unit on another bus, two requests for use of the one and another buses are issued substantially at the same time, thereby reducing the time taken for acquiring a bus-using right of the another bus. As soon as it is found that access is directed to the second unit on the one bus, the request for using the another bus is canceled, thus reducing a bus occupation rate for the another bus.

Claims

1. A bus system comprising:

a first bus;

a first master unit and a first slave unit each connected to the first bus;

a first bus arbiter coupled to the first master unit for carrying out arbitration of a bus-using right of the first bus;

a second bus coupled to the first bus;

a second master unit and a second slave unit each connected to the second bus;

an address decoder connected to the second bus for decoding an address outputted to the second bus from the second master unit and for discriminating whether the second master unit is to access the first slave unit or the second slave unit based on the decoded address; and

a second bus arbiter coupled to the second master unit for carrying out arbitration of a bus-using right of the second bus, for outputting a bus-using request signal for the first bus to the first bus arbiter in response to a bus-using request signal outputted from the second master unit, and for discarding the bus-using request signal for the first bus to the first bus arbiter in response to a signal outputted from the address decoder indicating that the second master unit is to access the second slave unit.

2. An apparatus for controlling a bus-using right in a bus system wherein a first master unit, a second master unit, and at least one slave unit are connected to a common bus, said first master unit uses the common bus, and at least said second master unit accesses one slave unit of said at least one slave unit via the common bus to transfer data between said second master unit and said one slave unit at predetermined time intervals (T1) determined by said second master unit, the apparatus comprising:

first timer means responsive to said second master unit for determining when a predetermined time T2 (T2<

T1) has elapsed after said second master unit started one data transfer;

means responsive to said first timer means for issuing a bus-using request when the time T2 has elapsed after said second master unit started the one data transfer in order to acquire a bus-using right for the common bus for said second master unit in advance of said second master unit starting another data transfer;

means responsive to the bus-using request for granting the bus-using right for the common bus for said second master unit in advance of said second master unit starting the another data transfer, thereby allowing said second master unit to start the another data transfer immediately when the time T1 has passed after said second master unit started the one data transfer;

second timer means responsive to the bus-using request for determining when a predetermined time T3 (T2+T3>

T1) has elapsed after the bus-using request was issued; and

means responsive to said second timer means and said second master unit for discarding the bus-using right granted in advance when said second master unit has not started the another data transfer when the time T3 has elapsed after the bus-using request was issued.

3. A bus system with a plurality of units connected to a common bus, wherein at least one unit of the units uses the common bus at predetermined timings, the bus system comprising:

a bus arbiter coupled to each of said units for carrying out arbitration of a bus-using right of the common bus;

first timer means for measuring a first time period indicative of a timing at which said one unit will next begin to use the common bus and for producing a first output signal when the first time period has been measured;

second timer means for measuring a second time period during which said one unit does not use the common bus and for producing a second output signal when the second time period has been measured; and

request control means connected to said one unit, said bus arbiter, said first timer means, and said second timer means for driving said first timer means to start measuring the first time period when said one unit begins to use the common bus, for generating a bus-using request to said bus arbiter in response to the first output signal from said first timer means, for driving said second timer means to start measuring the second time period when the bus-using request is issued, for resetting the second timer means if said one unit begins to use the common bus before the second timer produces the second output signal, and for cancelling the bus-using request if said second timer means produces the second output signal before said one unit begins to use the common bus.