Trench planarization techniques

• US 5,298,110 A
• Filed: 11/20/1992
• Issued: 03/29/1994
• Est. Priority Date: 06/06/1991
• Status: Expired due to Term

• Current Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Pasch, Nicholas F., Schoenborn, Philippe
• Primary Examiner(s): DANG, THI D
• Application Number:
  US07/979,792
• Time in Patent Office: 494 Days
• Field of Search: 156/626, 156/627, 156/645, 156/636, 437/8
• US Class Current: 438/5
• CPC Class Codes: H01L 21/3105 After-treatment
• CPC Class Codes: H01L 21/31053 involving a dielectric removal step
• CPC Class Codes: H01L 21/7621 the recessed region having a shape other than rectangular, e.g. rounded or oblique shape H01L21/76208 takes precedence
• CPC Class Codes: H01L 21/76227 the dielectric materials being obtained by full chemical transformation of non-dielectric materials, such as polycristalline silicon, metals
• CPC Class Codes: H01L 21/76235 trench shape altered by a local oxidation of silicon process step, e.g. trench corner rounding by LOCOS
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/5283 Cross-sectional geometry
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H05K 1/115 Via connections; Lands around holes or via connections H05K1/112 takes precedence
• CPC Class Codes: H05K 3/4644 by building the multilayer layer by layer, i.e. build-up multilayer circuits making via holes in the insulating layers H05K3/0011; special circuit boards as base or core whereon the multilayer is built H05K3/4602
• CPC Class Codes: Y10S 438/959 Mechanical polishing of wafer

Abstract

Various techniques for quantifying polishing performance are disclosed, and provide insight on the progression from a planarization regime to a smoothing regime to a blanket polish back regime, as well as providing a single, definable parameter (Quality Characteristic) for optimizing polishing performance. With these analytical tools in hand, it is possible to create novel structures which absorb polish rate non-uniformities across a wafer, and it is also possible to define and employ a "quick" polish step to clear high spots which will be followed by a subsequent etch step for rapid removal of material.

Claims

1. A method of polishing irregular features of a semiconductor device top surface topography, comprising:

polishing a sample specimen having first trench features;

measuring the height (h) and width (W) of the first trench features during polishing;

calculating the feature aspect ratio (FAR=h/w) of the first trench features;

measuring the rate of removal (Ri) inside the first trench features and outside (Ro) the first trench features during polishing;

calculating a Relative Polish Rate (RPR=Ri/Ro);

plotting first feature width (W), RPR, and FAR; and

polishing a semiconductor device having second features similar to the first trench features of the sample specimen, based on results graphically observed in the plot of first feature polishing.

2. A method of polishing a semiconductor device, according to claim 1, wherein:

polishing the semiconductor device proceeds from a planarization regime to a smoothing regime to a blanket polish back regime.

3. A method of polishing a semiconductor device, according to claim 2, wherein:

polishing the semiconductor device proceeds in the planarization regime while the RPR is near zero;

polishing the semiconductor device proceeds in the smoothing regime when all parts of the top surface of the semiconductor device are being removed at different rates; and

polishing the semiconductor device proceeds in the blanket polish back regime when all parts of the top surface of the semiconductor device are being removed at a substantially equal rate.

4. A method of polishing a semiconductor device, according to claim 1, wherein:

the second features are trenches in an insulating layer overlying a trenched substrate.

5. A method of polishing a semiconductor device, according to claim 4, wherein:

the second features are trenches in an LTO layer overfilling ROI trenches in the substrate.

6. A method of forming flush-filled trenches in a semiconductor device, comprising

forming a trench of depth h in a test specimen;

over-filling the trench with trench-fill material, so that the trench is at least full and there is excess material outside of the trench;

measuring the thickness (t_out) of the trench-fill material outside of the trench;

measuring the thickness (t_in) of the trench-fill material inside the trench;

defining a figure of merit (67 , where;

TI δ

=(t_in /h)(1-t_out /t_in);

polishing the test specimen for various intervals of time;

at each interval, remeasuring t_out and t_in ;

calculating the standard deviation σ

₆₇ , at each interval of time;

compounding the figure of merit δ and

the standard deviation σ

into a Quality Characteristic Q that reflects the overall process performance; and

polishing a semiconductor device having second trenches similar to the trenches in the test specimen based on the Quality Characteristic.

7. A method according to claim 6, wherein:

the Quality Characteristic is calculated as follows;

space="preserve" listing-type="equation">Q=Ln(f(δ

)/σ

.sub.δ

);

f(δ

=1/t 2π

)e.sup.-1/2((δ

-1)/t)

and wherein "t " is a tolerance factor on δ

.

8. A method according to claim 7, wherein:

the second trenches are troughs in an insulating layer overlying a trenched substrate.

9. A method according to claim 8, wherein:

the second trenches are troughs in an LTO layer overfilling ROI trenches in the substrate.