Method for testing semiconductor devices
First Claim
1. A method for manufacturing semiconductor devices, comprising:
- a wafer manufacturing step of forming an integrated circuit with a redundant circuit and a power supply terminal in each of a plurality of chip areas on a semiconductor wafer and also forming at least one stress testing terminal that applies a stress testing voltage or stress testing signal to the interconnections other than those for power supply in said integrated circuit for each of the chip areas;
a step of, after the wafer manufacturing step, screening failures by applying a specified stress testing control signal or stress voltage to a certain number of chip areas with said stress testing terminal in contact with a contact terminal of a tester in the wafer state;
a step of, after the screening step, judging whether or not the electrical characteristics of each chip area are acceptable through test;
a step of remedying an integrated circuit in a chip area judged to be defective in the judging step, by means of said redundant circuit; and
an assembly step of, after the remedying step, separating said chip areas into individual elements and then assembling them into an integrated circuit device.
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Accused Products
Abstract
A method for manufacturing semiconductor devices according to this invention, comprises the wafer manufacturing step of forming an integrated circuit with a redundant circuit in each of a plurality of chip areas on a semiconductor wafer and also forming at least one stress testing terminal that applies a stress testing voltage or stress testing signal to the interconnections other than those for power supply in the integrated circuit for each of the chip areas or for every certain number of the chip areas, the step of, after the wafer manufacturing step, screening failures by applying a specified stress testing control signal or stress voltage to a certain number of chip areas with the stress testing terminal in contact with a contact terminal of a tester in the wafer state, the step of, after the screening step, judging whether or not the electrical characteristics of each chip area are acceptable through die sort test, the step of remedying an integrated circuit in a chip area judged to be defective in the judging step, by means of the redundant circuit, and the assembly step of, after the remedying step, separating the chip areas into individual elements and then assembling them into an integrated circuit device.
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Citations
26 Claims
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1. A method for manufacturing semiconductor devices, comprising:
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a wafer manufacturing step of forming an integrated circuit with a redundant circuit and a power supply terminal in each of a plurality of chip areas on a semiconductor wafer and also forming at least one stress testing terminal that applies a stress testing voltage or stress testing signal to the interconnections other than those for power supply in said integrated circuit for each of the chip areas; a step of, after the wafer manufacturing step, screening failures by applying a specified stress testing control signal or stress voltage to a certain number of chip areas with said stress testing terminal in contact with a contact terminal of a tester in the wafer state; a step of, after the screening step, judging whether or not the electrical characteristics of each chip area are acceptable through test; a step of remedying an integrated circuit in a chip area judged to be defective in the judging step, by means of said redundant circuit; and an assembly step of, after the remedying step, separating said chip areas into individual elements and then assembling them into an integrated circuit device. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A method for manufacturing semiconductor devices, comprising:
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a wafer manufacturing step of forming an integrated circuit with a redundant circuit and a power supply terminal in each of a plurality of chip areas on a semiconductor wafer and also forming a stress testing terminal that applies a stress testing voltage or stress testing signal to interconnections other than those for power supply in said integrated circuit for every certain number of said chip areas; a step of, after the wafer manufacturing step, screening failures by applying a specified stress testing control signal or stress voltage to a certain number of chip areas with said stress testing terminal in contact with a terminal of a tester in the wafer state; a step of, after the screening step, judging whether or not the electrical characteristics of each chip area are acceptable through a test; a step of remedying an integrated circuit in a chip area judged to be defective in the judging step, by means of said redundant circuit; and an assembly step of, after the remedying step, separating said chip areas into individual elements and then assembling them into an integrated circuit. - View Dependent Claims (16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26)
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Specification