Method for testing semiconductor devices

• US 5,298,433 A
• Filed: 12/26/1991
• Issued: 03/29/1994
• Est. Priority Date: 12/27/1990
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Furuyama, Tohru
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): HORTON, KENNETH
• Application Number:
  US07/813,511
• Time in Patent Office: 824 Days
• Field of Search: 437/8, 357/71, 365/200-201, 365/202, 365/230, 148/DIG. 162, 257/48
• US Class Current: 438/6
• CPC Class Codes: G01R 31/2831 Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates G01R31/318511 takes precedence; testing during manufacture H01L22/00
• CPC Class Codes: G01R 31/2856 Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM]
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: G01R 31/30 Marginal testing, e.g. by varying supply voltage testing computers during standby operation or idle time G06F11/22
• CPC Class Codes: Y10S 148/162 Testing steps

Abstract

A method for manufacturing semiconductor devices according to this invention, comprises the wafer manufacturing step of forming an integrated circuit with a redundant circuit in each of a plurality of chip areas on a semiconductor wafer and also forming at least one stress testing terminal that applies a stress testing voltage or stress testing signal to the interconnections other than those for power supply in the integrated circuit for each of the chip areas or for every certain number of the chip areas, the step of, after the wafer manufacturing step, screening failures by applying a specified stress testing control signal or stress voltage to a certain number of chip areas with the stress testing terminal in contact with a contact terminal of a tester in the wafer state, the step of, after the screening step, judging whether or not the electrical characteristics of each chip area are acceptable through die sort test, the step of remedying an integrated circuit in a chip area judged to be defective in the judging step, by means of the redundant circuit, and the assembly step of, after the remedying step, separating the chip areas into individual elements and then assembling them into an integrated circuit device.

Claims

1. A method for manufacturing semiconductor devices, comprising:

a wafer manufacturing step of forming an integrated circuit with a redundant circuit and a power supply terminal in each of a plurality of chip areas on a semiconductor wafer and also forming at least one stress testing terminal that applies a stress testing voltage or stress testing signal to the interconnections other than those for power supply in said integrated circuit for each of the chip areas;

a step of, after the wafer manufacturing step, screening failures by applying a specified stress testing control signal or stress voltage to a certain number of chip areas with said stress testing terminal in contact with a contact terminal of a tester in the wafer state;

a step of, after the screening step, judging whether or not the electrical characteristics of each chip area are acceptable through test;

a step of remedying an integrated circuit in a chip area judged to be defective in the judging step, by means of said redundant circuit; and

an assembly step of, after the remedying step, separating said chip areas into individual elements and then assembling them into an integrated circuit device.

2. A method for manufacturing semiconductor devices according to claim 1, further comprising a step of selecting chips to which a voltage stress is to be applied for failure screening, this step being located between said wafer manufacturing step and failure screening step.

3. A method for manufacturing semiconductor devices according to claim 1, further comprising a step of screening failures caused in said assembly step in the package state after assembly.

4. A method for manufacturing semiconductor devices according to claim 2, further comprising a step of screening failures caused in said assembly step, in the package state after assembly.

5. A method for manufacturing semiconductor devices according to any one of claims 1 to 4, wherein said integrated circuit is a memory circuit having a memory cell and a cell peripheral circuit, and performs said screening of failures in said memory cell and the screening of failures in said cell peripheral circuit in the package state after said assembly step.

6. A method for manufacturing semiconductor devices according to any one of claims 1 to 4, wherein said integrated circuit contains a circuit designed so as to be more active or more subjected to stress than during normal operation in the finished product state when said interconnections are externally applied with the stress testing control signal or stress voltage via said stress testing terminals.

7. A method for manufacturing semiconductor devices according to any one of claims 1 to 4, wherein said specified interconnections are directly or indirectly connected in common to all of or more than the interconnections selectively activated during normal operation in the finished product state, and are externally applied with a desired stress voltage via said stress testing terminal.

8. A method for manufacturing semiconductor devices according to claim 7, wherein said interconnections selectively activated during normal operation are interconnections selectively activated by the signal decoded from the address signal or by the scanning signal.

9. A method for manufacturing semiconductor devices according to claim 8, wherein said chip area is a memory chip area or a memory-incorporated chip area containing a memory circuit, and said interconnections connected in common to said specified interconnections are the word lines and/or bit lines of the memory cell array in said integrated circuit area.

10. A method for manufacturing semiconductor devices according to any one of claims 1 to 4, wherein said chip area contains a step-up circuit that steps up the power supply voltage input and supplies the stepped-up output only to some of the circuits during normal operation in the finished product state, and a control circuit that causes said step-up circuit to reduce the potential of the stepped-up output, make it equal to the potential before the step-up, or stop the step-up operation when said specified interconnections are externally applied with the stress testing control signal via said stress testing terminal.

11. A method for manufacturing semiconductor devices according to claim 10, wherein said chip area is a dynamic memory chips area or a memory-incorporated chip area containing a dynamic memory circuit, and said step-up circuit is a word-line voltage step-up circuit.

12. A method for manufacturing semiconductor devices according to any one of claims 1 to 4, wherein said chip area is a memory chip area or a memory incorporated chip area containing a memory circuit, which has a refresh address counter and a control circuit that controls said address counter so that the word lines of the memory cell array may be more active than in a refreshing action during normal operation in the finished product state when said interconnections are externally applied with the stress testing control signal via said stress testing terminal.

13. A method for manufacturing semiconductor devices according to any one of claims 1 to 4, wherein a certain number of said stress testing terminals are provided for each of said chip areas, in such a manner that they concentrate almost along one side of the chip area.

14. A method for manufacturing semiconductor devices according to any one of claims 1 to 4, wherein said semiconductor wafer is a semiconductor substrate or a substrate in which a semiconductor layer is formed on an insulating layer.

15. A method for manufacturing semiconductor devices, comprising:

a wafer manufacturing step of forming an integrated circuit with a redundant circuit and a power supply terminal in each of a plurality of chip areas on a semiconductor wafer and also forming a stress testing terminal that applies a stress testing voltage or stress testing signal to interconnections other than those for power supply in said integrated circuit for every certain number of said chip areas;

a step of, after the wafer manufacturing step, screening failures by applying a specified stress testing control signal or stress voltage to a certain number of chip areas with said stress testing terminal in contact with a terminal of a tester in the wafer state;

a step of, after the screening step, judging whether or not the electrical characteristics of each chip area are acceptable through a test;

a step of remedying an integrated circuit in a chip area judged to be defective in the judging step, by means of said redundant circuit; and

an assembly step of, after the remedying step, separating said chip areas into individual elements and then assembling them into an integrated circuit.

16. The method for manufacturing semiconductor devices according to claim 15, further comprising a pre-die sort step of selecting chips to which a voltage stress is to be applied for failure screening, the pre-die sort step occurring between the wafer manufacturing step and the failure screening step.

17. The method for manufacturing semiconductor devices according to claim 15, further comprising a step of screening failures caused in the assembly step in the package state after assembly.

18. The method for manufacturing devices according to claim 16, further comprising a step of screening failures caused in the assembly step in the package state after assembly.

19. The method for manufacturing semiconductor devices according to any one of claims 15-18, wherein said integrated circuit is a memory circuit having a memory cell and a cell peripheral circuit, and performs the screening of failures in said memory cell and the screening of failures in said cell peripheral circuit in the package stage after the assembly step.

20. The method for manufacturing semiconductor devices according to any one of claims 15-18, wherein said integrated circuit contains a circuit designed so as to be more active or more subjected to stress than during normal operation in the finished product state when said interconnections are externally applied with the stress testing control signal or stress voltage via said stress testing terminals.

21. The method for manufacturing semiconductor devices according to any one of claims 15-18, wherein said specified interconnections are directly or indirectly connected in common to all or more than the interconnections selectively activated during normal operation in the finished product state, and are externally applied with a desired stress voltage via said stress testing terminal.

22. The method for manufacturing semiconductor devices according to claim 21, wherein said interconnections selectively activated during normal operation are interconnections selectively activated by a signal decoded from an address signal or by a scanning signal.

23. The method for manufacturing semiconductor devices according to claim 22, wherein said chip area is a memory chip area or a memory-incorporated chip area containing a memory circuit, and said interconnections connected in common to said specified interconnections are word lines and/or bit lines of the memory cell array in said integrated circuit area.

24. The method for manufacturing semiconductor devices according to any one of claims 15-18, wherein said chip area contains a step-up circuit that steps up the power supply voltage input and supplies the stepped-up output only to some of the circuits during normal operation in the finished product state, and a control circuit that causes said step-up circuit to reduce the potential of the stepped-up output, make it equal to the potential before the step-up, or stop the step-up operation when said specified interconnections are externally applied with the stress testing control signal via said stress testing terminal.

25. The method for manufacturing semiconductor devices according to claim 24, wherein said chip area is a dynamic memory chip area or a memory-incorporated chip area containing a dynamic memory circuit, and said step-up circuit is a word line voltage step-up circuit.

26. The method of manufacturing semiconductor devices according to any one of claims 15-18, wherein said chip area is a memory chip area or a memory-incorporated chip area containing a memory circuit, which has a refresh address counter and a control circuit that controls said address counter so that the word lines of the memory cell array may be more active than in a refreshing action during normal operation in the finished product state when said interconnections are externally applied with the stress testing control signal via said stress testing terminal.