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Method for testing semiconductor devices

  • US 5,298,433 A
  • Filed: 12/26/1991
  • Issued: 03/29/1994
  • Est. Priority Date: 12/27/1990
  • Status: Expired due to Term
First Claim
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1. A method for manufacturing semiconductor devices, comprising:

  • a wafer manufacturing step of forming an integrated circuit with a redundant circuit and a power supply terminal in each of a plurality of chip areas on a semiconductor wafer and also forming at least one stress testing terminal that applies a stress testing voltage or stress testing signal to the interconnections other than those for power supply in said integrated circuit for each of the chip areas;

    a step of, after the wafer manufacturing step, screening failures by applying a specified stress testing control signal or stress voltage to a certain number of chip areas with said stress testing terminal in contact with a contact terminal of a tester in the wafer state;

    a step of, after the screening step, judging whether or not the electrical characteristics of each chip area are acceptable through test;

    a step of remedying an integrated circuit in a chip area judged to be defective in the judging step, by means of said redundant circuit; and

    an assembly step of, after the remedying step, separating said chip areas into individual elements and then assembling them into an integrated circuit device.

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