Trench DMOS power transistor with field-shaping body profile and three-dimensional geometry

• US 5,298,442 A
• Filed: 09/18/1991
• Issued: 03/29/1994
• Est. Priority Date: 12/27/1988
• Status: Expired due to Term

• Current Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Original Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Inventors: Bulucea, Constantin, Rossen, Rebecca
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): MASON, DAVID
• Application Number:
  US07/762,103
• Time in Patent Office: 923 Days
• Field of Search: 437/29, 437/40, 437/41, 437/203, 437/23.6, 437/38, 437/39, 437/958, 357/23.4, 148/126, 257/328
• US Class Current: 438/270
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/4232 with insulated gate
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: Y10S 148/126 Power FETs

Abstract

Power MOSFET apparatus, and method for its production, that suppresses voltage breakdown near the gate, using a polygon-shaped trench in which the gate is positioned, using a shaped deep body junction that partly lies below the trench bottom, and using special procedures for growth of gate oxide at various trench corners.

Claims

1. A method for providing a trench DMOS transistor cell, the method comprising the steps of:

providing a substrate of semiconductor material of heavily doped first electrical conductivity type having a top surface;

providing a first covering layer of semiconductor material of first electrical conductivity type having a top surface and being contiguous to and overlying the substrate top surface;

providing a second covering layer of semiconductor material of second electrical conductivity type having a top surface and being contiguous to the top surface of the first covering layer and extending vertically downward from the top surface of the first covering layer into an upper portion of the first covering layer;

providing a third covering layer of semiconductor material of heavily doped first electrical conductivity type having a top surface and being contiguous to and partly overlying the top surface of the second covering layer, where a portion of the second covering layer is heavily doped and this portion extends vertically upward through the third covering layer to the top surface thereof and forms an exposed pattern of the second covering layer in the top surface of the third covering layer, and where the maximum depth of the heavily doped portion of the second covering layer relative to the top surface of the third covering layer is a depth d₁ ;

providing a trench having side walls and bottom walls and extending vertically downward from the top surface of the third covering layer through the third and second covering layers and through a portion of, but not all of, the first covering layer, where the trench has a maximum depth relative to the top surface of the third covering layer equal to a second depth d₂ and d₂ is less than d₁, where the trench in horizontal cross section is approximately a polygonal stripe, and where this polygonal stripe laterally surrounds and is spaced apart from the exposed pattern of the second covering layer at the top surface of the third covering layer;

providing a layer of oxide positioned within the trench and contiguous to the bottom walls and side walls of the trench so that portions, but not all, of the trench are filled with the oxide layer;

providing electrically conducting semiconductor material, contiguous to the oxide layer and positioned within the trench so that the oxide layer lies between the electrically conducting semiconductor material and the bottom and side walls of the trench; and

providing three electrodes that are electrically coupled to the electrically conducting semiconductor material in the trench, to the third covering layer and to the substrate, respectively,

wherein the difference d₁ -d₂ of said first and second depths d₁ and d₂ is sufficient to force junction breakdown away from the trench and into the heavily doped portion of the second covering layer.

2. The method according to claim 1, further comprising the step of providing said trench with rounded edges of oxidized material, where said bottom surfaces and said side surfaces of said trench meet and where said side surfaces of said trench meet said top surface of said third covering layer and where said side surfaces of said trench meet with one another.

3. A method for providing a vertical DMOS transistor, the method comprising the steps of:

providing a substrate;

providing an epitaxial layer above the substrate;

providing a trench in the epitaxial layer, the trench having a predetermined depth d_u ; and

providing a body region in the epitaxial layer, the body region having a predetermined maximum depth d_max,

wherein the depth d_u is less than the depth d_max, and

wherein the difference between the depth d_max and the depth d_u is sufficient to force junction breakdown away from the trench and into the epitaxial layer.

4. The method of claim 3 wherein the substrate is of a first conductivity type, the epitaxial layer is of said first conductivity type and the body region is of a second conductivity type.

5. The method of claim 4 wherein the epitaxial layer has a top surface and the body region extends from the epitaxial layer top surface into an upper portion of the epitaxial layer.

6. The method of claim 5 wherein a source region is formed in said epitaxial layer.

7. The method of claim 6 wherein a heavily doped epitaxial region partially covers the body region.

8. The method of claim 7 wherein the body region includes a heavily doped body region extending upward through the heavily doped epitaxial region and forming an exposed pattern at the epitaxial layer top surface.

9. The method of claim 8 wherein the trench surrounds the exposed pattern of the heavily doped body region.

10. The method of claim 3 wherein the trench has side walls and further comprising the steps of:

providing an oxide layer on the trench walls; and

etching the oxide layer to create a trench having rounded corners.

11. The method of claim 10 further comprising the steps of providing a gate oxide layer within the trench.

12. The method of claim 11 further comprising the step of providing electrically conducting material contiguous to the oxide layer, wherein the oxide layer is located between the electrically conducting material and the trench.

13. The method of claim 11 further comprising the steps of:

forming a first polysilicon layer on a portion of said oxide layer;

forming a second oxide layer on a portion of said first polysilicon layer;

forming a second polysilicon layer on a portion of said second oxide layer; and

depositing a metal layer wherein said second polysilicon layer extends from the trench to a field region creating an electrical contact to the metal layer and providing continuity from the metal layer to the trench.

14. The method of claim 3 further comprising the step of providing electrical contact to the gate region, the drain region and simultaneously to the body region and the source region.

15. The method of claim 3 wherein a horizontal cross section of the cell has a polygonal shape.

16. The method of claim 13 wherein the polygonal shape becomes circular during the method steps.

17. A method for providing a transistor, said method comprising the steps of:

providing a first region of a first conductivity type;

providing a second region of a second conductivity type over said first region;

providing a third region of said first conductivity type such that said first and third regions are separated by said second region;

providing a trench through said third and second regions; and

providing a gate in said trench;

wherein a portion P of said second region, which portion is spaced from said trench, extends deeper than said trench so that, if a predetermined voltage is applied to said gate and to said third region and another predetermined voltage is applied to said first region, an avalanche breakdown occurs away from a surface of said trench.

18. The method of claim 17 wherein said portion P of said second region is doped heavier than another portion of said second region which portion is adjacent said trench.

19. The method of claim 17 wherein said first region comprises a first portion and a second portion over said first portion, said second portion being lighter doped than said first portion.

20. The method of claim 19 wherein said avalanche breakdown is a reach-through breakdown across said second portion.

21. The method of claim 17 wherein said portion P of said second region extends deeper than said trench by more than 0.5 μ

m.

22. The method of claim 17 further comprising the step of providing an insulator between said surface of said trench and said gate.

23. A method for providing a transistor, said method comprising the steps of:

providing a first region of a first conductivity type;

providing a second region of said first conductivity type over said first region, said second region being lighter doped than said first region;

providing a third region of a second conductivity type over said second region, said second and third regions forming a junction;

providing a fourth region of said first conductivity type over said third region;

providing a trench through said fourth and third regions; and

providing a gate in said trench;

wherein a deepest part of said third region is laterally spaced from said trench; and

wherein a distance between said deepest part of said third region and said first region is less than a depletion width of a planar junction which has the same doping profile as does said junction between said second and third regions at said deepest part of said third region and which is reverse biased around its breakdown voltage.

24. The method of claim 23 wherein said deepest part of said third region is doped heavier than a part of said third region which part is adjacent said trench.