Semiconductor device and method of fabricating same

• US 5,298,780 A
• Filed: 11/24/1992
• Issued: 03/29/1994
• Est. Priority Date: 02/17/1992
• Status: Expired due to Term

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Harada, Masana
• Primary Examiner(s): WOJCIECHOWICZ, EDWARD JOSEPH
• Application Number:
  US07/980,691
• Time in Patent Office: 490 Days
• Field of Search: 257/330, 257/332, 257/333, 257/336, 257/405, 257/655, 437/90, 437/105, 437/141, 437/164, 437/203, 437/233, 437/913
• US Class Current: 257/330
• CPC Class Codes: H01L 21/2255 the applied layer comprising oxides only, e.g. P2O5, PSG, H3BO3, doped oxides
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

There is disclosed a semiconductor device having a vertical channel MOS gate structure wherein grooves (40) are formed from the top surface of source regions (5) through a body (3) into an N diffusion region (2) and wherein buried gate electrodes (4) fill an inner part of said grooves (40) which is in face-to-face relation to the N diffusion region (2) across gate oxide films (13) while buried oxide films (15) including diffusion source impurities fill an inner part thereof which is in face-to-face relation to the source regions (5). The impurity concentration of the source regions (5) is distributed uniformly in the vertical direction of the grooves (40) and decreases lateraly away from the grooves (40). A current flows through the source region along the grooves and a resistance thereagainst is held small in an ON-state. The grooves may be formed with narrow spacing. The size reduction and high integration of the semiconductor device are achieved as well as reduction in ON-resistance.

Claims

1. A semiconductor device comprising:

a first semiconductor layer of a first conductivity type having first and second major surfaces;

a second semiconductor layer of a second conductivity type formed on said first major surface;

a third semiconductor layer of the first conductivity type selectively formed on said second semiconductor layer;

a groove extending from a top surface of said third semiconductor layer through said second semiconductor layer into said first semiconductor layer;

a dielectric layer formed at least on an inner wall of said groove which is in face-to-face relation to said second semiconductor layer;

a control electrode formed on said inner wall of said groove through said dielectric layer; and

an insulating layer formed on a part of an inner wall of said groove which is in face-to-face relation to said third semiconductor layer and containing an impurity of the first conductivity type,

a portion of said third semiconductor layer adjacent to said groove having a uniform impurity concentration in the vertical direction along said groove.

2. The semiconductor device of claim 1, wherein said dielectric layer is further formed on an inner wall of said groove which is in face-to-face relation to said first semiconductor layer.

3. The semiconductor device of claim 2,

wherein said control electrode fills a region surrounded by said dielectric layer, and

wherein said insulating layer fills said groove associated with said dielectric layer and said control electrode.

4. The semiconductor device of claim 3, wherein said impurity concentration of said third semiconductor layer decreases lateraly away from said insulating layer.

5. The semiconductor device of claim 4, further comprising

a fourth semiconductor layer of the first conductivity type formed on said second major surface of said first semiconductor layer, the impurity concentration of said fourth semiconductor layer being higher than that of said first semiconductor layer.

6. The semiconductor device of claim 5, further comprising

a first electrode formed on an surface of said fourth semiconductor layer.

7. The semiconductor device of claim 6, further comprising

a second electrode formed at least on said top surface of said third semiconductor layer.

8. The semiconductor device of claim 7, wherein said third semiconductor layer surrounds at least said insulating layer.

9. The semiconductor device of claim 8, wherein said second electrode short-circuits said second and third semiconductor layers.

10. The semiconductor device of claim 1, further comprising

a fourth semiconductor layer of the second conductivity type formed on said second major surface of said first semiconductor layer, the impurity concentration of said fourth semiconductor layer being higher than that of said second semiconductor layer.

11. A method of fabricating a semiconductor device, comprising the steps of:

(a) providing a first semiconductor layer of a first conductivity type having first and second major surfaces;

(b) forming a second semiconductor layer of a second conductivity type on said first major surface;

(c) forming a groove extending through from a top surface of said second semiconductor layer into said first semiconductor layer, said groove having a first region in the vicinity of said top surface of said second semiconductor layer and a second region other than said first region;

(d) forming a dielectric layer on an inner wall of said groove in said second region;

(e) forming a control electrode on said dielectric layer;

(f) forming an insulating layer containing a diffusion source impurity of the first conductivity type at least on an inner wall of said groove in said first region; and

(g) diffusing said diffusion source impurity from said insulating layer to selectively form a third semiconductor layer of the first conductivity type in contact with said groove on said second semiconductor layer, said third semiconductor layer being at least longer than said first region in the direction of the thickness of said second semiconductor layer.

12. The method of claim 11,

wherein said step (a) includes the step of

(a-1) forming said first semiconductor layer by epitaxial growth on a fourth semiconductor layer having an impurity concentration higher than the impurity concentration of said first semiconductor layer, said second major surface being an interface of said fourth and first semiconductor layers.

13. The method of claim 11,

wherein said step (b) includes the step of

(b-1) introducing an impurity of the second conductivity type from said first major surface.

14. The method of claim 11,

wherein said step (c) includes the steps of:

(c-1) forming a first oxide film above said second semiconductor layer;

(c-2) selectively removing and leaving said first oxide film; and

(c-3) etching said second semiconductor layer by using said left first oxide film as a mask.

15. The method of claim 14,

wherein said step (c-1) includes the steps of:

(c-1-1) forming a second oxide film on said second semiconductor layer;

(c-1-2) forming a nitride film on said second oxide film; and

(c-1-3) forming said first oxide film on said nitride film, and

wherein said step (c-2) includes the step of

(c-2-1) selectively leaving said nitride film and said second oxide film in the same configuration as said left first oxide film.

16. The method of claim 15,

wherein said step (d) includes the steps of:

(d-1) exposing said nitride film; and

(d-2) oxidizing an inside of said groove.

17. The method of claim 11,

wherein said step (e) includes the steps of:

(e-1) forming a conductive film all over a structure provided in said steps (a) to (d) to fill said groove; and

(e-2) removing said conductive film, with said conductive film left unremoved only in said second region,

said conductive film left in said second region in said step (e-2) being equivalent to said control electrode.

18. The method of claim 17,

wherein said conductive film is a polycrystalline semiconductor, and

wherein said step (e-2) includes the steps of:

(e-2-1) leveling said conductive film;

(e-2-2) oxidizing said conductive film in said first region; and

(e-2-3) removing said oxidized conductive film as well as said dielectric layer in said first region.

19. The method of claim 17,

wherein said step (e) further includes the step of

(e-3) removing said dielectric layer in said first region.

20. The method of claim 15,

wherein said step (f) includes the steps of:

(f-1) forming said insulating layer all over a structure provided in said steps (a) to (e) to fill said first region; and

(f-2) leveling said insulating layer.

21. The method of claim 20,

wherein said step (f) further includes, prior to said step (f-1), the step of

(f-3) removing said nitride film.