Vertical current flow field effect transistor with thick insulator over non-channel areas

• US 5,298,781 A
• Filed: 07/08/1992
• Issued: 03/29/1994
• Est. Priority Date: 10/08/1987
• Status: Expired due to Term

• Current Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Original Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Inventors: Blanchard, Richard A., Cogan, Adrian I.
• Primary Examiner(s): Hille, Rolf
• Assistant Examiner(s): LOKE, STEVEN HO YIN
• Application Number:
  US07/910,864
• Time in Patent Office: 629 Days
• Field of Search: 257/327, 257/329, 257/330, 257/333, 257/344, 257/408
• US Class Current: 257/333
• CPC Class Codes: H01L 21/32137 of silicon-containing layers
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66484 with multiple gate, at least one gate being an insulated gate H01L29/66742 takes precedence
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/739 controlled by field-effect, e.g. bipolar static induction transistors [BSIT] unijunction transistors H01L29/705
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/7832 the structure comprising a MOS gate and at least one non-MOS gate, e.g. JFET or MESFET gate
• CPC Class Codes: Y10S 438/981 Utilizing varying dielectric thickness

Abstract

A transistor includes an N+ substrate, an N- region formed on the N+ substrate, a P- body region formed on the N- region, and an N+ source region formed on the P- body region. A vertical groove extends through the N+, P- and N- regions, and an insulating layer is formed on the groove walls. A polysilicon gate is formed inside the groove. Of importance, the portion of the insulating layer between the polysilicon and the N+ region and the insulating layer between the polysilicon and the N+ substrate is thicker than the portion of the insulating layer between the polysilicon gate and the P- body region. Because of the enhanced thickness of the portions of the insulating layer between the gate and N+ substrate, the transistor constructed in accordance with our invention is less susceptible to premature field induced breakdown.

Claims

1. A transistor comprising:

a P-type first semiconductor region;

an N-type second semiconductor region formed on said first semiconductor region;

a P-type third semiconductor region formed on said second semiconductor region;

a trench extending through said third and second semiconductor regions at least to said first semiconductor region;

an insulating layer formed on the walls of said trench, a portion of said insulating layer adjacent said first semiconductor region being thicker than a portion of said insulating layer adjacent said second semiconductor region; and

a gate formed in said trench, said gate being insulated from said first, second and third semiconductor regions by said insulating layer,

wherein a portion of said insulating layer adjacent said third semiconductor region is thicker than said portion of said insulating layer adjacent said second semiconductor region.

2. The transistor of claim 1 wherein said first semiconductor region comprises a first portion and a second portion formed on said first portion, the dopant concentration in said second portion being less than the dopant concentration in said first portion, said trench extending through at least part of said second portion.

3. A transistor comprising:

a first semiconductor region of a first conductivity type;

a second semiconductor region of a second conductivity type opposite said first conductivity type formed on said first semiconductor region;

a third semiconductor region of said first conductivity type formed on said second semiconductor region;

a trench extending through said third and second semiconductor regions at least to said first semiconductor region;

an insulating layer formed on the walls of said trench, a portion of said insulating layer adjacent said first semiconductor region being at least five time thicker than a portion of said insulating layer adjacent said second semiconductor region; and

a gate formed in said trench, said gate being insulated from said first, second and third semiconductor regions by said insulating layer,

wherein a portion of said insulating layer adjacent said third semiconductor region is at least five times thicker than said portion of said insulating layer adjacent said second semiconductor region.

4. A transistor comprising:

a first semiconductor region of a first conductivity type;

p1 a second semiconductor region of a second conductivity type opposite said first conductivity type formed on said first semiconductor region;

a third semiconductor region of said first conductivity type formed on said second semiconductor region;

a trench extending through said third and second semiconductor regions at least to said first semiconductor region;

an insulating layer formed on the walls of said trench, a portion of said insulating layer adjacent said third semiconductor region being at least five times thicker than a portion of said insulating layer adjacent said second semiconductor region; and

a gate formed in said trench, said gate being insulated from said first, second and third semiconductor regions by said insulating layer.

5. A transistor comprising:

a first semiconductor region of a first conductivity type;

a second semiconductor region of a second conductivity type opposite said first conductivity type formed on said first semiconductor region, said second semiconductor region comprising a first portion and a second portion;

a third semiconductor region of said first conductivity type formed on said second semiconductor region;

a trench extending through said semiconductor region and said first and second portions of said second semiconductor region at least to said first semiconductor region;

an insulating layer formed on the walls of said trench, a portion of said insulating layer adjacent said third semiconductor region and said second portion of said second semiconductor region being thicker than a portion of said insulating layer adjacent said first portion of said second semiconductor region; and

a gate formed in said trench, said gate being insulated from said first, second and third semiconductor regions by said insulating layer.

6. A transistor comprising:

a first semiconductor region of a first conductivity type;

a second semiconductor region of said first conductivity type and of a dopant concentration less than a dopant concentration of said first semiconductor region, said second semiconductor region formed on said first semiconductor region, said second semiconductor region comprising a first portion and a second portion;

a third semiconductor region of a second conductivity type opposite said first conductivity type formed on said second semiconductor region;

a fourth semiconductor region of said first conductivity type formed on said third semiconductor region;

a trench extending through said fourth and third semiconductor regions and said first and second portions of said second semiconductor region at least to said first semiconductor region;

an insulating layer formed on the wall of said trench such that a first portion of said insulating layer which portion is adjacent said first semiconductor region and also adjacent said first portion of said second semiconductor region is thicker than a second portion of said insulating layer which portion is adjacent said second portion of said second semiconductor region and also adjacent said third semiconductor region; and

a gate formed in said trench, said gate being insulated from said first, second, third and fourth semiconductor regions by said insulating layer.

7. The transistor of claim 6 wherein said first portion of said insulating layer is at least five times thicker than said second portion of said insulating layer.

8. The transistor of claim 6 wherein:

said third region comprises a first portion and a second portion;

said second portion of said insulating layer is adjacent said first portion of said third semiconductor region; and

a third portion of said insulating layer adjacent said fourth semiconductor region and also adjacent said second portion of said third semiconductor region is thicker than said second portion of said insulating layer.

9. The transistor of claim 8 wherein each of said first and third portions of said insulating layer is at least five times thicker than said second portion of said insulating layer.