Semiconductor embedded layer technology including permeable base transistor

• US 5,298,787 A
• Filed: 04/01/1991
• Issued: 03/29/1994
• Est. Priority Date: 08/10/1979
• Status: Expired due to Term

• Current Assignee: Bio-Oxidation Services Incorporated
• Original Assignee: Massachusetts Institute of Technology
• Inventors: Murphy, R. Allen, Alley, Gary D., Lindley, William T., Bozler, Carl O.
• Primary Examiner(s): Hille, Rolf
• Assistant Examiner(s): LOKE, STEVEN HO YIN
• Application Number:
  US07/678,670
• Time in Patent Office: 1,093 Days
• Field of Search: 357/22 E, 357/22 V, 357/22 G, 357/22 GR, 357/22 R, 357/15, 357/23.14, 257/263, 257/266, 257/270, 257/273, 257/74, 257/506, 257/472, 257/523, 257/617, 257/208, 257/211, 257/774, 257/776, 257/609, 257/592, 257/552, 257/555
• US Class Current: 257/592
• CPC Class Codes: H01L 21/02395 Arsenides
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/02639 Preparation of substrate for selective deposition
• CPC Class Codes: H01L 21/743 Making of internal connections, substrate contacts
• CPC Class Codes: H01L 23/4824 Pads with extended contours, e.g. grid structure, branch structure, finger structure
• CPC Class Codes: H01L 23/52 Arrangements for conducting electric current within the device in operation from one component to another , i.e. interconnections, e.g. wires, lead frames optical interconnections G02B6/00
• CPC Class Codes: H01L 23/535 including internal interconnections, e.g. cross-under constructions internal lead connections H01L23/481
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H01L 29/66424 Permeable base transistors [PBT]
• CPC Class Codes: H01L 29/7722 using static field induced regions, e.g. SIT, PBT
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

A permeable base transistor (30) including a metal base layer (34) embedded in a semiconductor crystal (32) to separate collector (38) and emitter (40) regions and form a Schottky barrier with each is diclosed. The metal base layer has at least one opening (37) through which the crystal semiconductor (32) joins the collector (38) and emitter (40) regions. Ohmic contacts (42,44) are made to the emitter (38) and collector (40) regions. The width of all openings (37) in the base layer (34) is of the order of the zero bias depletion width corresponding to the carrier concentration in the opening. The thickness of the metal layer (34) is in the order of 10% of this zero bias depletion width. As a result, a potential barrier in each opening limits current flow over the lower portion of the bias range. With increasing forward base bias the potential in the openings, which is lower than along the metal of the base layer (34), is lowered sufficiently to permit substantial increase in the barrier limited current flow from the collector (38) to emitter (40).

Claims

1. An active semiconductor device comprising:

a thin metal base layer embedded in a semiconductor single crystal and providing a metal-semiconductor potential barrier between emitter and collector regions,

the metal base layer having at least one opening therein through which semiconductor single crystal extends, substantially all of the openings being dimensioned such that the ratio of metal layer thickness to opening width is less than one-half to permit barrier limited current flow therethrough within an operating range of base biasing, the barrier being sufficient at some base biasing level to virtually eliminate current flow through the openings, the normalized transconductance g_m /I_c of the device being greater than 2 volt^-1 over a range of collector current.

2. An active semiconductor device comprising:

a thin metal layer embedded in semiconductor single crystal material to separate single crystal regions and form a potential barrier;

the metal layer having at least one opening therein through which semiconductor single crystal material joins the crystal regions, substantially all openings in the metal layer having the same controlled width in the order of the zero bias depletion width of the barrier; and

the thickness of the metal layer being in the order of 10% of the zero bias depletion width.

3. An active semiconductor device as claimed in claim 2 wherein the openings are slits.

4. An active semiconductor device as claimed in claim 3 wherein the opening widths are less than the zero bias depletion width in the semiconductor and are greater than 10% of that depletion width.

5. An active semiconductor device as claimed in claim 2 wherein the metal base layer includes at least two sets of coplanar interleaved metal fingers, each set being connected to a separate input.

6. An active semiconductor device as claimed in claim 2 wherein the total open area of the metal base layer is at least about 10 percent of the total area of the metal base layer across the active portion of the device.

7. An active semiconductor device as claimed in claim 2 wherein a plurality of openings having uniform widths are uniformly spaced across the device.

8. An active semiconductor device as claimed in claim 2 having only a single opening in the metal base layer.

9. An active semiconductor device as claimed in claim 2 wherein the opening widths are greater than 10 percent of the zero bias depletion width in the semiconductor and less than twice the zero bias depletion width.

10. An active semiconductor device as claimed in claim 9 wherein the opening widths are less than the zero bias depletion width.

11. An active semiconductor device as claimed in claim 2 including a concentration gradient in the semiconductor crystal.

12. An active semiconductor device as claimed in claim 2, in combination with a plurality of like active semiconductor devices, at least some of the interconnections between said plurality of active semiconductor devices being extensions of metal base layers and also being embedded in a semiconductor material.

13. An active semiconductor device as claimed in claim 2, in combination with a plurality of like active semiconductor devices, in a stacked configuration within a semiconductor material.

14. A plurality of active semiconductor devices as claimed in claim 13 wherein two stacked active semiconductor devices share a common semiconductor region.

15. A plurality of active semiconductor devices as claimed in claim 13 wherein at least some of the interconnections between said plurality of active semiconductor devices are completely embedded within the semiconductor material.

16. A plurality of active semiconductor devices as claimed in claim 15 wherein the embedded interconnections include extensions of metal base layers and ohmic contacts.

17. A plurality of active semiconductor devices as claimed in claim 16 wherein the semiconductor material is gallium arsenide and said plurality of active semiconductor devices are isolated by proton bombardment of the gallium arsenide.

18. A plurality of active semiconductor devices as claimed in claim 13 including a metal layer forming a Schottky barrier in an unused semiconductor region below one of said plurality of active semiconductor devices to provide isolation.

19. An active semiconductor device as claimed in claim 2, in combination with a plurality of like active semiconductor devices, including complementary devices formed in adjacent n and p type regions.

20. An active semiconductor device as claimed in claim 2 wherein substantially all current flow between the crystal regions, within an operating range of base biasing, is barrier limited current flow through the openings, the normalized transconductance g_m /I_c of the device being greater than 2 volts^-1 over a range of collector current.

22. A transistor device as claimed in claim 3 wherein substantially all emitter-collector current flow, within an operating range of base biasing, is barrier limited current flow through the openings, the normalized transconductance g_m /I_c of the device being greater than 2 volts^-1 over a range of collector current.

21. A transistor device comprising:

single crystal semiconductor material having emitter and collector regions; and

a metal base layer embedded in the single crystal semiconductor material, the metal base layer having at least one slit opening therein through which single crystal semiconductor material joins the emitter and collector regions, the width of substantially all slits in the active portion of the base layer being in the order of the zero bias depletion width of a potential barrier between the metal and semiconductor.

23. A transistor device comprising:

a thin metal base layer embedded in a semiconductor crystal between emitter and collector contacts and providing a metal - semiconductor potential barrier;

the metal base layer having a plurality of slit openings therein through which single crystal semiconductor material joins the emitter and collector regions, the width of substantially all slits in the active portion of the base layer being uniform and equal and in the order of the zero bias depletion width of the barrier;

the thickness of the metal base layer being in the order of 10% of the zero bias depletion width; and

substantially all emitter-collector current flow through the device being barrier limited current flow through the slits within an operating range of base biasing.

24. A transistor device as claimed in claim 23 wherein the normalized transconductance g_m /I_c of the device is greater than 2 volts^-1 over a range of collector current.

25. An active semiconductor device comprising:

an emitter semiconductor region;

a collector semiconductor region;

a base region including at least two sets of coplanar interleaved control fingers extending across the device between the emitter and collector regions, each set being connected to a separate input to control current flow between the emitter and base regions.

26. An active semiconductor device as claimed in claim 25 wherein the interleaved fingers are metal and are spaced by a width in the order of the zero biased depletion width of a Schottky barrier formed between the fingers and the semiconductor regions and the fingers have a thickness in the order of 10 percent of the zero bias depletion width of the semiconductor between the fingers.

27. An active semiconductor device as claimed in claim 25 wherein the carrier concentration in the semiconductor regions and the finger and interspacial widths are such that the device functions as a logic circuit.

28. An active semiconductor device as claimed in claim 25 including an AC input to each of the sets of coplanar interleaved fingers such that one input modulates the output due to the other input.

29. An active semiconductor device as claimed in claim 25 including a DC input to one set of fingers to provide gain control with respect to an AC input to the other set of fingers.

30. A single semiconductor chip integrated circuit comprising a plurality of devices in a stacked configuration, at least some of the interconnections between devices being totally embedded within the semiconductor chip, the plurality of devices including devices having metal base layers embedded in the semiconductor, at least some of the embedded interconnections being extensions of said metal base layers.

31. A single semiconductor chip integrated circuit as claimed in claim 30 wherein the interconnections have openings therein through which semiconductor crystal has been grown.

32. A single semiconductor chip integrated circuit as claimed in claim 30 including interconnections which are extensions of ohmic contacts, the contacts being embedded between devices.

33. A single semiconductor chip integrated circuit as claimed in claim 30 wherein devices are isolated by heavy particle bombardment of the semiconductor material.

34. A single semiconductor chip integrated circuit as claimed in claim 30 wherein the semiconductor material is gallium arsenide and transistor devices are isolated by proton bombardment of the gallium arsenide.

35. A single semiconductor chip integrated circuit as claimed in claim 30 including current limiting devices in one layer associated in a stacked configuration with transistor devices in another layer.

36. A single semiconductor chip integrated circuit as claimed in claim 35 wherein the current limiting devices are saturated resistors.

37. A single semiconductor chip integrated circuit as claimed in claim 30 including negative resistance devices in one layer associated in a stacked configuration with transistor devices in another layer.

38. A single semiconductor chip integrated circuit as claimed in claim 30 wherein stacked devices share a common semiconductor region.

39. A single semiconductor chip integrated circuit as claimed in claim 30 including an embedded non-semiconducting layer serving as isolation for at least one of said devices.

40. A single semiconductor chip integrated circuit as claimed in claim 39 wherein the non-semiconducting layer is metal and forms a Schottky barrier with the semiconductor.

41. A single semiconductor chip integrated circuit as claimed in claim 39 wherein the non-semiconducting layer is an insulator.

42. A single semiconductor chip integrated circuit comprising a plurality of devices, including devices having metal base layers embedded in the semiconductor, at least some of the interconnections between said devices being extensions of the metal base layers totally embedded within the semiconductor chip.

43. A single semiconductor chip integrated circuit comprising a plurality of devices, at least some of the interconnections between said plurality of devices being totally embedded within the semiconductor chip, the integrated circuit further comprising an embedded metal layer which forms a Schottky barrier with the semiconductor and serves as isolation for at least one of said plurality of devices.

44. A single semiconductor chip integrated circuit comprising an embedded non-semiconducting layer embedded within the semiconductor chip below a semiconductor device as isolation for the device wherein the non-semiconducting layer is metal and forms a Schottky barrier with the semiconductor.

45. A single semiconductor chip integrated circuit as claimed in claim 44 wherein the non-semiconducting layer has openings therein through which semiconductor crystal has been grown.