BiCMOS CMOS/ECL data multiplexer

• US 5,298,810 A
• Filed: 09/11/1992
• Issued: 03/29/1994
• Est. Priority Date: 09/11/1992
• Status: Expired due to Term

• Current Assignee: Sampsons Group LLC (Intellectual Ventures LLC)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Scott, Paul H., Williams, Bertrand J.
• Primary Examiner(s): Westin, Edward P.
• Assistant Examiner(s): ROSEEN, RICHARD R
• Application Number:
  US07/943,932
• Time in Patent Office: 564 Days
• Field of Search: 307/475, 307/473, 307/446, 307/296.1, 307/243
• US Class Current: 326/66
• CPC Class Codes: H03K 17/6264 using current steering means
• CPC Class Codes: H03K 19/017527 with at least one differential stage
• CPC Class Codes: H03K 19/086 Emitter coupled logic

Abstract

An ECL circuit with power control is disclosed. The ECL circuit comprises a pair of emitter-coupled transistors with a current source transistor having its collector coupled to the coupled-emitters of the pair. Coupled in series with the base of the current source transistor is a first MOS transistor with its gate receiving an enable signal to control the first MOS transistor. As such, an activated first MOS transistor switches on the ECL circuit, and a de-activated first MOS transistor switches off the ECL circuit with no current through the current source transistor to provide a true power down of the ECL circuit. An ECL circuit for translating from CMOS to ECL levels is also disclosed. The ECL circuit comprises a pair of emitter-coupled transistors and first MOS transistor coupled in series with a first base of the pair at one end of the source/drain current path of the first MOS transistor. Another end of the source/drain current path of the first MOS transistor is coupled to a current-source voltage, while its gate receives an enable signal. Coupled in series with a second base of the pair at one end of the source/drain current path of the second MOS transistor is a second MOS transistor. Another end of the source/drain current path of the second MOS transistor is also coupled to the current-source voltage, while its gate receives an inverted enable signal. Thus, the pair has its two emitter-coupled transistors alternately switched on by the enable and inverted enable signals. An ECL circuit for multiplexing ECL inputs with CMOS select signals is further disclosed. The ECL circuit comprises the top portion of a conventional ECL multiplexer connected to a pair of Vcs current sources. The current sources are alternately selected by the N-channel MOS transistor coupled between the Vcs current source and one base of the n-p-n transistors.

Claims

1. An ECL circuit with power control, said ECL circuit comprising:

a pair of emitter-coupled transistors of a first conductive type, said pair coupled to an input and an inverted input at the bases of said pair, the collectors of said pair being coupled to a first voltage;

current source transistor having its collector coupled to the coupled-emitters of said pair and its emitter coupled to a second voltage;

first MOS transistor having a source/drain current path coupled in series with the base of said current source transistor, one end of said source/drain current path of said first MOS transistor being coupled to the base of said current source transistor and the other end of said source/drain current path of said first MOS transistor being coupled to a current source voltage, the gate of said first MOS transistor receiving an enable signal to control the state of said first MOS transistor,

wherein an activated first MOS transistor switches on said ECL circuit, and a de-activated first MOS transistor switches off said ECL circuit with no current through said current source transistor to provide a true power down of said ECL circuit.

2. An ECL circuit according to claim 1, wherein the switching speeds of said ECL circuit is critical, further comprising shunting means coupled across the base and emitter of said current source transistor.

3. An ECL circuit according to claim 2, wherein said shunting means comprises:

second MOS transistor having a source/drain current path coupled across the base and emitter of said current source transistor at two ends of said source/drain current path of said second MOS transistor, the gate of said second MOS transistor receiving an inverted enable signal to control the state said second MOS transistor,

wherein an activated first MOS transistor and a de-activated second MOS transistor switch on said ECL circuit, and a de-activated first MOS transistor and an activated second MOS transistor switch off said ECL circuit with no current through said current source transistor.

4. An ECL circuit according to claim 1, wherein transistors in said first conductive type are n-p-n transistors.

5. An ECL circuit with power control according to claim 3, wherein transistors in said first conductive type are n-p-n transistors.

6. An ECL circuit with power control according to claim 5, further comprising:

first output transistor of said first conductive type having its base coupled to a first collector of said pair and its collector coupled to the first voltage, the emitter of said first output transistor generating an output signal;

second output transistor of said first conductive type having its base coupled to a second collector of said pair and its collector coupled to the first voltage, the emitter of said second output transistor generating an inverted output signal.

7. An ECL circuit with power control according to claim 6, further comprising a CMOS inverter for generating said inverted enable signal from said enable signal.

8. An ECL circuit for translating from CMOS to ECL levels, said ECL circuit comprising:

a pair of emitter-coupled transistors of a first conductive type having their collectors coupled to a first voltage and their emitters coupled to ground;

first MOS transistor having a source/drain current path coupled in series with a first base of said pair at one end of said source/drain current path of said first MOS transistor, the other end of said source/drain current path of said first MOS transistor being coupled to a current-source voltage, its gate receiving an enable signal;

second MOS transistor having a source/drain current path coupled in series with a second base of said pair at one end of said source/drain current path of said second MOS transistor, the other end of said source/drain current path of said second MOS transistor being coupled to said current-source voltage, its gate being coupled to an inverted enable signal, wherein said pair has its two emitter-coupled transistors alternately switched on by said enable and said inverted enable signals.

9. An ECL circuit according to claim 8, further comprising:

first shunting means coupled across said first base and said coupled-emitters of said pair; and

second shunting means coupled across said second base and said coupled-emitters of said pair.

10. An ECL circuit according to claim 9, wherein:

said first shunting means comprises third MOS transistor coupled across said first base and said coupled emitters of said pair, the gate of said third MOS transistor being coupled to said inverted enable signal, and

said second shunting means comprises fourth MOS transistor coupled across said second base and said coupled emitters of said pair, its gate being coupled to said enable signal.

11. An ECL circuit according to claim 9, wherein:

said first shunting means is a relatively high value resistor, and

said second shunting means is a high value resistor for not critical turn-on and turn-off speed of said ECL circuit.

12. An ECL circuit according to claim 9, further comprising a CMOS inverter for generating said inverted enable signal from said enable signal such that a logic cell containing said ECL circuit is single-ended.

13. An ECL circuit according to claim 12, wherein said first conductive type is n-p-n type.

14. An ECL circuit according to claim 11, further comprising a CMOS inverter for generating said inverted enable signal from said enable signal such that a logic cell containing said ECL circuit is single-ended.

15. An ECL circuit according to claim 14, wherein said first conductive type is n-p-n type.

16. A single-ended ECL circuit for translating from CMOS to ECL levels, comprising:

first transistor of a first conductive type, the collector of said first transistor coupled to a first voltage and the emitter of said first transistor coupled to a second voltage;

first MOS transistor coupled in series between the base of said first transistor and a current-source voltage, the gate of said first MOS transistor receiving an enable signal to control the state of said first MOS transistor such that currents through said first transistor are shut off when said first MOS transistor is switched off,

wherein an inverted output of said single-ended ECL circuit is generated at the collector of said first transistor.

17. A single-ended ECL circuit according to claim 16, further comprising second MOS transistor coupled across the base and emitter of said first transistor for shunting, the gate of said second MOS transistor receiving an inverted enable signal to control the state of said second MOS transistor.

18. A single-ended ECL circuit according to claim 17, wherein said first conductive type is n-p-n type.

19. A CML circuit for multiplexing CML inputs with CMOS select signals, said CML circuit comprising:

first pair of emitter-coupled transistors of a first conductive type with their collectors coupled to a first voltage, the bases of said first pair receiving a first and inverted first inputs;

second pair of emitter-coupled transistors of said first conductive type with their collectors coupled to said first voltage, the bases of said second pair receiving a second and inverted second inputs;

third pair of emitter-coupled transistors of said first conductive type with the collector of a first transistor of said third pair coupled to the emitters of said first pair and the collector of a second transistor of said third pair coupled to the emitters of said second pair, the emitters of said third pair being coupled to a second voltage;

first MOS transistor coupled in series between the base of said first transistor of said third pair and a current-source voltage, the gate of said MOS transistor receiving a select signal to control the state of said first MOS transistor;

second MOS transistor coupled in series between the base of said second transistor of said third pair and said current-source voltage, the gate of said second MOS transistor receiving an inverted select signal to control the state of said second MOS transistor;

wherein said first and second MOS transistors are alternately turned on by said select signal to switch on one of said first and second pair of emitter-coupled transistors to generate an output and an inverted output at the collectors of one of said first and second pair.

20. A CML circuit according to claim 19, further comprising shunting means, said shunting means comprising:

third MOS transistor coupled across the base of said first transistor and the emitters of said third pair, the gate of said third MOS transistor receiving said inverted select signal;

fourth MOS transistor coupled across the base of said second transistor and the emitters of said third pair, the gate of said fourth MOS transistor receiving said select signal,

wherein said select signal switches on one of said first and second pairs of emitter-coupled transistors to generate an output and an inverted output at the collectors of one of said first and second pair by turning on one of said first and said second MOS transistors.

21. A CML circuit according to claim 20, wherein said first conductive type is n-p-n conduction.