System and method for producing a palette of many colors on a display screen having digitally-commanded pixels

• US 5,298,915 A
• Filed: 06/16/1992
• Issued: 03/29/1994
• Est. Priority Date: 04/10/1989
• Status: Expired due to Term

• Current Assignee: ATI Technologies Incorporated (Advanced Micro Devices, Inc.)
• Original Assignee: Cirrus Logic Incorporated
• Inventors: Bassetti, Chester F. Jr.
• Primary Examiner(s): BRIER, JEFFERY A
• Application Number:
  US07/899,267
• Time in Patent Office: 651 Days
• Field of Search: 340/701, 340/703, 340/767, 340/793
• US Class Current: 345/696
• CPC Class Codes: G09G 2320/0247 Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
• CPC Class Codes: G09G 2320/0261 in the context of movement of objects on the screen or movement of the observer relative to the screen
• CPC Class Codes: G09G 2320/0266 Reduction of sub-frame artefacts
• CPC Class Codes: G09G 2320/0276 for the purpose of adaptation to the characteristics of a display device, i.e. gamma correction
• CPC Class Codes: G09G 2360/18 Use of a frame buffer in a display terminal, inclusive of the display panel
• CPC Class Codes: G09G 3/20 for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
• CPC Class Codes: G09G 3/2003 Display of colours specific for liquid crystal displays G09G3/3607
• CPC Class Codes: G09G 3/2007 Display of intermediate tones
• CPC Class Codes: G09G 3/2025 the sub-frames having all the same time duration
• CPC Class Codes: G09G 3/2051 with use of a spatial dither pattern
• CPC Class Codes: G09G 3/2092 Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto suitable for both CRT and flat panel G09G5/003; specific for a CRT G09G1/165
• CPC Class Codes: G09G 3/3611 Control of matrices with row and column drivers
• CPC Class Codes: H04N 3/127 using liquid crystals

Abstract

An apparatus is disclosed for controlling primary color producing sub-pixels of a digitally commanded display to provide mixed colors in which sub-pixels are controlled over a programmable number N of consecutive frames to be either ON or OFF during each of the frames so that a desired time averaged brightness is produced of the primary color associated with each sub-pixel, and so that the combination of the produced time averaged brightnesss results in the color desired for the pixel to which the sub-pixels belong. The apparatus employs a modulo-N adder for programmably controlling each primary color sub-pixel by using a frame rate duty cycle approach.

Claims

1. An apparatus for controlling a pixel on a digitally commanded display to produce a mixed color, the pixel having a positional value within an array of pixels on the digitally commanded display, wherein the mixed color is formed from specified primary colors, each having a specified brightness, and wherein the pixel comprises a plurality of colored sub-pixels, each of which provides a different one of the specified primary colors, the apparatus including:

programmable control means for controlling each sub-pixel using a frame rate duty cycle approach to produce a programmable number N of time averaged brightnesses over N consecutive frames, such that the sub-pixel is commanded by a pixel drive signal to be either ON or OFF during each frame of the N consecutive frames, the programmable control means comprising;

brightness waveform memory means for storing a plurality of brightness waveforms wherein a command value from one of the plurality of stored brightness waveforms is selected in response to a phase value signal and is supplied as the pixel drive signal to command the sub-pixel to be either ON or OFF;

addressing means for determining the positional value of the pixel within the array and a current frame number, and for supplying the positional value and the current frame number as outputs; and

means for providing the phase value signal as a function of a modulo-N operation on a sum of the positional value and current frame number.

2. The apparatus of claim 1 wherein the phase signal providing means further includes:

adding means for providing an output which is the sum of the positional value and the current frame number; and

dividing means for dividing the output of the adding means by the programmable number N, and for outputting a quotient and a remainder, where the remainder is supplied as the phase value signal.

3. The apparatus of claim 1, wherein each of the plurality of brightness waveforms commands the sub-pixel for the associated color towards an ON state during a specified number of the N consecutive frames, and commands the sub-pixel towards an OFF state during the remainder of the N consecutive frames.

4. The apparatus of claim 1 wherein the positional address means includes:

phase placement memory means for storing a plurality of wrap around patterns, each pattern being a predetermined number of pattern values in length, and for outputting a pattern value from a selected wrap around pattern as the positional value; and

means for selecting the pattern value as a function of the position of the pixel within the array.

5. An apparatus for controlling a pixel on a digitally commanded display to produce a mixed color, the pixel having a positional value within an array of pixels on the digitally commanded display, wherein the mixed color is formed from specified primary colors, each having a specified brightness, and wherein the pixel comprises a plurality of colored sub-pixels, each of which provides a different one of the specified primary colors, the apparatus including:

programmable control means for controlling each sub-pixel using a frame rate duty cycle approach to produce a programmable number N of time averaged brightnesses over N consecutive frames, such that the sub-pixel is commanded by a pixel drive signal to be either ON or OFF during each frame of the N consecutive frames, the programmable control means comprising;

brightness waveform memory means for storing a plurality of brightness waveforms wherein a command value from one of the plurality of stored brightness waveforms is selected in response to a phase value signal and is supplied as the pixel drive signal to command the sub-pixel to be either ON or OFF;

positional address means for determining the positional value of the pixel within the array, and for supplying the positional value as an output signal;

a frame counting means for maintaining a count corresponding to a current frame number, the count being incremented when a new frame is begun, wherein the count is supplied as the current frame number, and further wherein the count is reset to 0 when N is reached; and

means for providing the phase value signal as a function of a modulo-N operation on a sum of the positional value and the current frame number.

6. The apparatus of claim 5 wherein the phase signal providing means further includes:

adding means for providing an output which is the sum of the positional value and the current frame number; and

dividing means for dividing the output of the adding means by the programmable number N, and for outputting a quotient and a remainder, where the remainder is supplied as the phase value signal.

7. The apparatus of claim 5 wherein the positional address means includes:

phase placement memory means for storing a plurality of wrap around patterns, each pattern being a predetermined number of pattern values in length, and for outputting an pattern value from a selected wrap around pattern as the positional value; and

means for selecting the pattern value as a function of the position of the pixel within the array.

8. The apparatus of claim 5, wherein each of the plurality of brightness waveforms commands the sub-pixel for the associated color towards an ON state during a specified number of the N consecutive frames, and commands the sub-pixel towards an OFF state during the remainder of the N consecutive frames.