Short locator method
First Claim
1. A computer implemented method for analyzing an electrical node of a circuit layout to locate erroneous connections thereon, the method comprising the steps of:
- forming a representation of the area of an electrical node including the erroneous connections therein for analysis;
segregating the area of the electrical node into a plurality of individual polygons oriented in contiguous array within said area wherein said step of segregating includes the substeps of;
identifying all obtuse angles along the perimeter of the area of the electrical node including the erroneous connections therein; and
forming alternate substantially horizontal and vertical divisions of the area of the electrical node at the locations of the obtuse angles in selected sequence along the perimeter of said area to form thereby a plurality of individual polygons in contiguous array; and
analyzing each individual polygon for proper connection to a contiguous polygon commencing from an initial starting point on a polygon within the area of the node.
5 Assignments
0 Petitions
Accused Products
Abstract
An improved circuit layout-verifying system and method operates on a plurality of polygons that are representative of an electrical node to test the proper or improper connection of each polygon to another contiguous polygon and designates for display those polygons that represent improper connections between known or identified reference points on the node. Traversals along a sequence of contiguous polygons between known reference points on the same electrical node are designated as proper connections or successes, and traversals along a sequence of contiguous polygon between reference points associated with different electrical nodes are designated as improper connections or failures at least along a portion of the sequence. Data from all traversals of all polygons from all known reference points is then analyzed to remove unambiguous sequences of polygons for the improperly connected electrical nodes. High resolution analysis is performed on large, single electrical nodes by selectively breaking down the node into subpolygons that can be analyzed in the previous manner.
32 Citations
7 Claims
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1. A computer implemented method for analyzing an electrical node of a circuit layout to locate erroneous connections thereon, the method comprising the steps of:
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forming a representation of the area of an electrical node including the erroneous connections therein for analysis; segregating the area of the electrical node into a plurality of individual polygons oriented in contiguous array within said area wherein said step of segregating includes the substeps of; identifying all obtuse angles along the perimeter of the area of the electrical node including the erroneous connections therein; and forming alternate substantially horizontal and vertical divisions of the area of the electrical node at the locations of the obtuse angles in selected sequence along the perimeter of said area to form thereby a plurality of individual polygons in contiguous array; and analyzing each individual polygon for proper connection to a contiguous polygon commencing from an initial starting point on a polygon within the area of the node. - View Dependent Claims (2, 3, 4, 5)
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6. A computer implemented method for analyzing an electrical node of a circuit layout to locate erroneous connections therein, the method comprising the steps of:
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forming a representation of the area of an electrical node including the erroneous connections therein for analysis; identifying a plurality of reference points in the area of the electrical node which are associated with at least two different electrical nodes; forming a plurality of contiguous polygons along and within the area of the electrical node at least between said reference points; traversing a sequence of polygons from one reference point toward another reference point on the electrical node to determine electrical connection of each polygon to an adjacent polygon previously traversed in the sequence, and storing the results of the determination for each polygon along the course of another reference point; designating success of connections in the stored results under conditions of the sequence proceeding between two reference points associated with the same electrical node, and designating failure of connections in the stored results under conditions of the sequence proceeding between two reference points associated with different electrical nodes; and displaying a representation of at least a portion of the sequence of polygons for which the stored results designate failure between two reference points. - View Dependent Claims (7)
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Specification