Circuit for preventing false programming of anti-fuse elements

• US 5,299,150 A
• Filed: 01/10/1989
• Issued: 03/29/1994
• Est. Priority Date: 01/10/1989
• Status: Expired due to Term

• Current Assignee: Actel Corporation (Microchip Technology Incorporated)
• Original Assignee: Actel Corporation (Microchip Technology Incorporated)
• Inventors: Ahrens, Michael G., Eltoukhy, Abdelshafy A., Galbraith, Douglas C., Hamdy, Esmat Z.
• Primary Examiner(s): Hecker, Stuart N.
• Assistant Examiner(s): Whitfield, Michael A.
• Application Number:
  US07/295,403
• Time in Patent Office: 1,904 Days
• Field of Search: 365/96, 365/189.06, 365/225.7, 365/174, 365/103, 365/104, 365/105, 365/230.06, 365/129
• US Class Current: 365/94
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: H01L 23/5252 comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H03K 19/17704 the logic functions being realised by the interconnection of rows and columns
• CPC Class Codes: H03K 19/1776 for memories
• CPC Class Codes: H03K 19/17764 for reliability
• CPC Class Codes: H03K 19/1778 Structural details for adapting physical parameters

Abstract

A circuit for preventing false programming of unselected anti-fuses in an anti-fuse array includes a series impedance including a plurality of transistors which may be used for partial address selection connected between a source of programming voltage and a bit line.

Claims

1. A read only memory array, including:

a plurality of two terminal anti-fuse elements, said two terminal anti-fuse elements being arranged in groups, each of said groups containing a number of said plurality of two terminal anti-fuse elements, have one terminal connected in common to a bit line,

a plurality of select transistors associated with each group of two terminal anti-fuse elements, each of said plurality of select transistors having a source, a drain, and a gate, the individual ones of said plurality of select transistors associated with each group having their sources commonly connected to a source of fixed voltage, said fixed voltage selected to between about 0.5 and 2 volts above ground, each one of said plurality of select transistors having its drain connected to the second terminal of a different two terminal anti-fuse element of said group of two terminal anti-fuse elements, and each one of said plurality of select transistors having its gate connected to one of a plurality of word lines,

a plurality of transistors connected in series between said bit line and an input/output line, each of said plurality of transistors having a gate coupled to a different one of a plurality of Y-select lines.

2. The read only memory of claim 1 wherein said plurality of transistors comprises a plurality of P-channel MOS transistors having their sources and drains connected in series between said input/output line and said bit line, respective gate of each of said plurality of P-channel MOS transistors connected to a different one of said plurality of Y-select lines.