Method for writing into semiconductor memory

• US 5,299,151 A
• Filed: 06/18/1991
• Issued: 03/29/1994
• Est. Priority Date: 06/22/1990
• Status: Expired due to Term

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Tanaka, Kenichi, Ishihara, Hiroshi, Sakiyama, Keizo
• Primary Examiner(s): James, Andrew J.
• Assistant Examiner(s): Tang, Alice W.
• Application Number:
  US07/716,785
• Time in Patent Office: 1,015 Days
• Field of Search: 365/225.7, 365/96, 257/50, 257/530, 257/529, 257/665
• US Class Current: 365/96
• CPC Class Codes: G11C 17/16 using electrically-fusible links

Abstract

A method is provided for writing into a semiconductor memory which includes a MOS transistor formed on a semiconductor substrate and an anti-fuse formed of an insulating film and an upper electrode on a drain of the MOS transistor. The method includes the steps of applying a first voltage between the upper electrode of the anti-fuse and a source of the MOS transistor to cause dielectric breakdown of the insulating film of the anti-fuse, with the MOS transistor turned on; and applying a second voltage between the upper electrode of the anti-fuse and the semiconductor substrate so that a larger amount of current flows than the amount of current required for breaking down the insulating film of the anti-fuse.

Claims

1. A method of writing into a semiconductor memory including a MOS transistor formed on a surface of a first conductivity type semiconductor substrate and an anti-fuse formed of an insulating film and an upper electrode on a drain of the MOS transistor, said MOS transistor having a source and the drain of a second conductivity type forming respective PN junctions with said semiconductor substrate, wherein the anti-fuse becomes conductive for storing data when a voltage across the drain and the upper electrode causes a dielectric breakdown of the insulating film, the method comprising the steps of:

applying a first voltage across the upper electrode of the anti-fuse and the source of the MOS transistor to cause the dielectric breakdown of the insulating film of the anti-fuse, when the MOS transistor is transistor is turned on; and

applying a second voltage across the upper electrode of the anti-fuse and the semiconductor substrate so that a larger amount of a second current than an amount of a first current required for breaking down the insulating film of the anti-fuse, flows between the upper electrode of the anti-fuse and the semiconductor substrate, said second voltage being of a polarity so as to forward bias the PN junction between the drain and the semiconductor substrate.

3. A method according to claim 1, wherein the MOS transistor comprises an N-channel type formed on a P-type semiconductor substrate,

the first voltage applies a positive potential to the upper electrode with respect to the source,

the second voltage applies a negative potential to the upper electrode with respect to the semiconductor substrate.

4. A method according to claim 1, wherein the MOS transistor comprises a P-channel type formed on an N-type semiconductor substrate,

the first voltage applies a negative potential to the upper electrode with respect to the source,

the second voltage applies a positive potential to the upper electrode with respect to the semiconductor substrate.

2. A method for writing into a semiconductor memory including a MOS transistor formed on a surface of a semiconductor substrate and an anti-fuse formed of an insulating film and an upper electrode on a drain of the MOS transistor, wherein the anti-fuse becomes conductive for storing data when a voltage across the drain and the upper electrode causes a breakdown of the insulating film, the method comprising the step of:

applying a first voltage across the upper electrode of the anti-fuse and a source of the MOS transistor to cause the dielectric breakdown of the insulating film of the anti-fuse, when the MOS transistor is turned on; and

subsequently applying a second voltage across the upper electrode of the anti-fuse and the semiconductor substrate such that a large amount of a second current than an amount of a first current required for breaking down the insulating film of the anti-fuse flows between the upper electrode of the anti-fuse and the semiconductor substrate, through the insulating film and the drain of the MOS transistor, said second voltage being of a polarity different from the first voltage.

5. A semiconductor memory, comprising:

a MOS transistor formed on a surface of a first conductivity type semiconductor substrate;

an anti-fuse formed of an insulating film and an upper electrode on a drain of the MOS transistor, said MOS transistor having a source and the drain of a second conductivity type forming respective PN junctions with said semiconductor substrate so that the anti-fuse becomes conductive for storing data when a voltage across the drain and the upper electrode causes a dielectric breakdown of the insulating film;

means for applying a first voltage across the upper electrode of the anti-fuse and the source of the MOS transistor to cause the dielectric breakdown of the insulating film of the anti-fuse, when the MOS transistor is turned on; and

means for applying a second voltage across the upper electrode of the anti-fuse and the semiconductor substrate so that a larger amount of a second current than an amount of a first current required for breaking down the insulating film of the anti-fuse, flows between the upper electrode of the anti-fuse and the semiconductor substrate, said second voltage being of a polarity so as to forward bias the PN junction between the drain and the semiconductor substrate.

6. A semiconductor memory according to claim 5, wherein the MOS transistor comprises an N-channel type formed on a P-type semiconductor substrate, said first voltage applies a positive potential to the upper electrode with respect to the source and said second voltage applies a negative potential to the upper electrode with respect to the semiconductor substrate.

7. A semiconductor memory according to claim 5, wherein the MOS transistor comprises a P-channel type formed on an N-type semiconductor substrate, said first voltage applies a negative potential to the upper electrode with respect to the source and said second voltage applies a positive potential to the upper electrode with respect to the semiconductor substrate.

8. A semiconductor memory, comprising:

a MOS transistor formed on a surface of a first conductivity type semiconductor substrate;

an anti-fuse formed of an insulating film and an upper electrode on a drain of the MOS transistor so that the anti-fuse becomes conductive for storing data when an application of a voltage across the drain and the upper electrode causes a dielectric breakdown of the insulating film;

means for applying a first voltage when the MOS transistor is turned on, across the upper electrode of the anti-fuse and a source of the MOS transistor to cause the dielectric breakdown of the insulating film of the anti-fuse;

means for subsequently applying a second voltage of a different polarity than the first voltage, across the upper electrode of the anti-fuse and the semiconductor substrate so that a larger amount of a second current than an amount of a first current required for breaking down the insulating film of the anti-fuse, flows between the upper electrode of the anti-fuse and the semiconductor substrate, through the insulating film and the drain of the MOS transistor.