Anti-fuse memory device with switched capacitor setting method

• US 5,299,152 A
• Filed: 01/28/1992
• Issued: 03/29/1994
• Est. Priority Date: 06/22/1990
• Status: Expired due to Term

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Tanaka, Kenichi, Ishihara, Hiroshi, Sakiyama, Keizo
• Primary Examiner(s): CLAWSON JR, JOSEPH
• Application Number:
  US07/827,073
• Time in Patent Office: 791 Days
• Field of Search: 365/96, 365/100, 365/102, 365/103, 365/104, 365/225.7, 257/530
• US Class Current: 365/96
• CPC Class Codes: H01L 23/5252 comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

A semiconductor device includes memory cells each of which include a plurality of groups of an anti-fuse and a transistor connected in series; a capacitor including first and second electrodes, with the first electrode connected to a bit line of the memory cell; a first switch connected between the bit line and a power source; a second switch connected between the power source and the second electrode of the capacitor; and a third switch connected between the second electrode of the capacitor and a ground. A specific memory cell is selected out of the memory cells, and a superposed supply voltage is applied through the capacitor to the anti-fuse of the specific memory by turning on and/or off the first through third switches, so that a storage of information in the memory cell can be performed.

Claims

1. A method of making a conduction by breaking down an anti-fuse in a semiconductor device that includes a plurality of anti-fuses and a capacitance with one capacitance electrode being connected to first terminals of the anti-fuses, the method comprising the steps of:

turning on a transistor connected between a second terminal of a specific anti-fuse and a basic potential for selecting the specific anti-fuse out of the plurality of anti-fuse;

impressing a first potential which have predetermined potential difference on one capacitance electrode and the first terminal of the specific anti-fuse, and setting the ground level on the other capacitance electrode so as to charge the one capacitance electrode, cutting off the first potential, and impressing a second potential on the other capacitance electrode,

thereby the first potential and the second potential being superposed on one capacitance electrode, applying the superposed potential to the first terminal of the specific anti-fuse to execute a conduction by the breakdown of the specific anti-fuse.

2. A method as claimed in claim 1, wherein the first and second potentials are of the same polarity.

3. A method as claimed in claim 1, wherein the first and second potentials are the same voltage as the power source.

4. A method as claimed in claim 1, wherein a combination of the anti-fuse and the transistor forms a unit memory cell, and the breakdown of one anti-fuse performs the storage of information into a memory cell.

5. A method as claimed in claim 1, wherein the basic potential is a ground level.