Semiconductor memory device with discriminator for diagnostic mode of operation

• US 5,299,163 A
• Filed: 06/15/1992
• Issued: 03/29/1994
• Est. Priority Date: 06/27/1991
• Status: Expired due to Term

• Current Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Original Assignee: NEC Corporation
• Inventors: Mortigami, Seiichi
• Primary Examiner(s): Popek, Joseph A.
• Assistant Examiner(s): Nguyen, Viet Q.
• Application Number:
  US07/898,119
• Time in Patent Office: 652 Days
• Field of Search: 371/21.4, 371/28, 365/201
• US Class Current: 365/201
• CPC Class Codes: G11C 29/46 Test trigger logic

Abstract

A semiconductor memory device is subjected to a test operation before delivery from the factory for screening defective products, and can be established in a diagnostic mode for carrying out the test operation when a discriminator acknowledges itself to be expected to produce an internal control signal for the test operation, wherein an instruction signal supplied to the discriminator has active level outside a predetermined voltage range for external signals for a standard access mode of operation so that the semiconductor memory device does not mistakenly enter the diagnostic mode after assembled in an electronic system, thereby preventing the electronic system from malfunction.

Claims

1. A semiconductor memory device having a standard mode for data access and a diagnostic mode for circuit components, said device comprising:

a) a memory cell array accessible in said standard mode with external signals, each of said external signals swinging its voltage level in a predetermined voltage range, and being subjected to a test operation in said diagnostic mode;

b) peripheral circuits for giving an external device access said memory cell array in said standard mode, and for carrying out said test operation in said diagnostic mode; and

c) a discriminator responsive to an instruction signal indicative of said test operation, for enabling said peripheral circuits to carry out said test operation, said instruction signal having an active level outside said predetermined voltage range, said discriminator comprising

c-1) a step-down circuit coupled with a test pin supplied with said instruction signal, and implemented by a first series combination of a load transistor of a first channel conductivity type and a resistive element coupled between a power voltage line and said test pin, said test pin being further coupled with the gate electrode of said load transistor,

c-2) a level discriminating circuit coupled with said step-down circuit for checking said test pin to see whether or not the voltage level at said test pin is outside said predetermined voltage range, and

c-3) a control signal generating circuit associated with said level discriminating circuit, and operative to produce a control signal indicative of said test operation when said level discriminating circuit confirms that the voltage level at the test pin is outside said predetermined voltage range.

2. A semiconductor memory device having a standard mode for data access and a diagnostic mode for circuit components, said device comprising:

a) a memory cell array accessible in said standard mode with external signals, each of said external signals swinging its voltage level in a predetermined voltage range, and being subjected to a test operation in said diagnostic mode;

b) peripheral circuits for giving an external device to access said memory cell array in said standard mode, and for carrying out said test operation in said diagnostic mode; and

c) a discriminator responsive to an instruction signal indicative of said test operation, and for enabling said peripheral circuits to carry out said test operation, said instruction signal having an active level outside said predetermined voltage range, said discriminator comprising

c-1) a step-down circuit coupled with a test pin supplied with said instruction signal, said step-down circuit comprising a series combination of a first resistive element, an intermediate node and a second resistive element coupled between a constant voltage line and said test pin where said instruction signal is applied,

c-2) a level discriminating circuit coupled with said step-down circuit for checking said test pin to determine whether or not the voltage level at said test pin is outside said predetermined voltage range, and

c-3) a control signal generating circuit associated with said level discriminating circuit, said control signal generating circuit being operative to produce a control signal indicative of said test operation when said level discriminating circuit confirms that the voltage level at the test pin is outside said predetermined voltage range.

3. A semiconductor memory device having a standard mode for data access and a diagnostic mode for circuit components, comprising:

a) a memory cell array accessible in said standard mode with external signals, each of said signals swinging its voltage level in a predetermined voltage range, and being subjected to a test operation in said diagnostic mode;

b) peripheral circuits for giving an external device to access said memory cell array in said standard mode, and for carrying out said test operation in said diagnostic mode; and

c) a discriminator responsive to an instruction signal indicative of said test operation, and for allowing said peripheral circuits to carry out said test operation, said instruction signal having an active level outside said predetermined voltage range, said discriminator comprising

c-1) a step-down circuit coupled with a test pin supplied with said instruction signal,

c-2) a level discriminating circuit coupled with said step-down circuit for checking said test pin to determine whether or not the voltage level at said test pin is outside said predetermined voltage range, said level discriminating circuit comprising a series combination of a p-channel enhancement type first transistor and an n-channel enhancement type second transistor coupled between a constant voltage line and an intermediate node, said constant voltage line being coupled with a gate electrode of said p-channel enhancement type first transistor and a gate electrode of said n-channel enhancement type second transistor, and

c-3) a control signal generating circuit associated with said level discriminating circuit, and operative to produce a control signal indicative of said test operation when said level discriminating circuit confirms that the voltage level at the test pin is outside said predetermined voltage range.