Circuit for detecting refresh address signals of a semiconductor memory device

• US 5,299,168 A
• Filed: 04/22/1993
• Issued: 03/29/1994
• Est. Priority Date: 04/22/1992
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kang, Kyung-Woo
• Primary Examiner(s): LaRoche, Eugene R.
• Assistant Examiner(s): GLEMBOCKI, CHRISTOPHE
• Application Number:
  US08/050,780
• Time in Patent Office: 341 Days
• Field of Search: 365/201, 365/222, 365/189.05, 365/233.5
• US Class Current: 365/222
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters

Abstract

Disclosed is a refresh address test circuit of a semiconductor memory device having a self-refresh function using a plurality of internal refresh address signals, comprising a plurality of the address test paths, each including a first sub-path which receives an initial logic level of one bit of an initial refresh address and a second sub-path of which receives successive corresponding bits of said refresh address, a plurality of comparators, each connected to the first sub-path and the second sub-path, a test output circuit receives the output signals generated from the plurality of comparators to determine whether a complete cycle of refresh addresses have been generated.

Claims

1. A semiconductor memory device having a self-refresh function, comprising:

a memory cell array including a plurality of memory cells;

selection means for selecting certain of said memory cells;

a refresh control circuit for generating a refresh clock;

a refresh address counter for successively generating a predetermined plurality of refresh addresses in response to said refresh clock;

means for applying said successive refresh addresses to said selection means; and

a refresh address test circuit which receives said successive refresh addresses to detect whether said predetermining plurality of refresh addresses has been generated.

2. A semiconductor memory device according to claim 1, wherein said refresh address test circuit comprises;

a plurality of comparators, each comparator receiving an initial state refresh address bit and successive state refresh address bits and outputting a successive plurality of

a test output circuit for receiving said successive plurality of output signals from said comparators, said test output circuit including an AND gate which ANDs together each plurality of output signals.

3. A semiconductor memory device according to claim 2, wherein said refresh address test circuit comprises:

a plurality of latch means for holding said initial state address bits of said refresh address; and

a plurality of switch means for transferring each of said initial state refresh address bits of said refresh address to an associated one of said comparators.

4. A semiconductor memory device according to claim 3, wherein each of said switch means is activated before each of said initial state refresh address bits is at a same logic level.

5. A semiconductor memory device according to claim 4 wherein said same logic level corresponds to a substantially zero voltage level.

6. A semiconductor memory device according to claim 3 wherein a Φ

1 clock signal activates each of said plurality of switch means.

7. A semiconductor memory device according to claim 2 wherein each of said plurality of comparators is activated upon receipt of a Φ

2 clock signal, said Φ

2 clock signal being activated after a change from said initial state address is detected.

8. A semiconductor memory device according to claim 1 wherein said memory array is arranged in a plurality of rows and a plurality of columns, said selection means selects successive ones of said plurality of rows, and each said successive refresh addresses corresponds to one of said plurality of rows.

9. A semiconductor memory device according to claim 1 wherein said refresh address test circuit generates an address test signal indicating that said plurality of successive addresses has been detected and further including means for outputting said address test signal.

10. A refresh address test circuit of a semiconductor memory having a self-refresh function that uses a plurality of successively generated internal refresh addresses comprising:

a plurality of address test paths, each test path including a first sub-path for storing an initial state refresh address bit and a second sub-path for transferring successive state refresh address bits of said refresh addresses;

a plurality of comparators, each receiving said initial state refresh address bit from said first sub-path and successive state refresh address bits from said second sub-path and outputting a successive plurality of output signals; and

a test output circuit for receiving the successive plurality output signals generated from said plurality of comparators to determine whether said predetermined plurality of refresh addresses has been generated.

11. A semiconductor memory device according to claim 10, wherein said refresh address test circuit comprises:

a plurality of latch means for holding said initial state address bits of said refresh address; and

a plurality of switch means for transferring each of said initial state refresh address bits of said refresh address to an associated one of said comparators.

12. A semiconductor memory device according to claim 10, wherein each of said comparators is activated before each of said refresh address bits is at a same logic level.