Circuit for detecting refresh address signals of a semiconductor memory device
First Claim
1. A semiconductor memory device having a self-refresh function, comprising:
- a memory cell array including a plurality of memory cells;
selection means for selecting certain of said memory cells;
a refresh control circuit for generating a refresh clock;
a refresh address counter for successively generating a predetermined plurality of refresh addresses in response to said refresh clock;
means for applying said successive refresh addresses to said selection means; and
a refresh address test circuit which receives said successive refresh addresses to detect whether said predetermining plurality of refresh addresses has been generated.
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Accused Products
Abstract
Disclosed is a refresh address test circuit of a semiconductor memory device having a self-refresh function using a plurality of internal refresh address signals, comprising a plurality of the address test paths, each including a first sub-path which receives an initial logic level of one bit of an initial refresh address and a second sub-path of which receives successive corresponding bits of said refresh address, a plurality of comparators, each connected to the first sub-path and the second sub-path, a test output circuit receives the output signals generated from the plurality of comparators to determine whether a complete cycle of refresh addresses have been generated.
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Citations
12 Claims
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1. A semiconductor memory device having a self-refresh function, comprising:
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a memory cell array including a plurality of memory cells; selection means for selecting certain of said memory cells; a refresh control circuit for generating a refresh clock; a refresh address counter for successively generating a predetermined plurality of refresh addresses in response to said refresh clock; means for applying said successive refresh addresses to said selection means; and a refresh address test circuit which receives said successive refresh addresses to detect whether said predetermining plurality of refresh addresses has been generated. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A refresh address test circuit of a semiconductor memory having a self-refresh function that uses a plurality of successively generated internal refresh addresses comprising:
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a plurality of address test paths, each test path including a first sub-path for storing an initial state refresh address bit and a second sub-path for transferring successive state refresh address bits of said refresh addresses; a plurality of comparators, each receiving said initial state refresh address bit from said first sub-path and successive state refresh address bits from said second sub-path and outputting a successive plurality of output signals; and a test output circuit for receiving the successive plurality output signals generated from said plurality of comparators to determine whether said predetermined plurality of refresh addresses has been generated. - View Dependent Claims (11, 12)
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Specification